Mixed Signal Receiver

Overview

The Mixed Signal Receiver project was built to capture analog signals and process them using FPGA-based digital signal processing. The system collects ADC data using microcontroller firmware, applies real-time filtering in the FPGA, and visualizes the processed signals using Python to analyze performance. I tested the receiver using several waveform types including sine waves, step inputs, pulse trains, and amplitude-modulated signals, which helped me gain experience working across hardware, firmware, and signal processing while building a complete mixed-signal system.

Problem & Constraints

The system was designed to capture and process analog signals while operating within hardware and signal limitations. The input signal was limited to 0–5 V to match the ADC requirements, and the analog front-end used a low-pass filter with a cutoff frequency of approximately 34 kHz to reduce noise. The ADC sampling rate was limited to 2 kHz, which restricted the maximum measurable signal frequency and required careful filter design. The FPGA DSP pipeline also needed to process data in real time while staying within available logic and memory resources.

My Role & Design

This was a personal project where I designed and built the full receiver system. I developed the analog filtering stage, wrote microcontroller firmware to capture ADC data, and implemented the digital filtering logic on the FPGA. I also created Python tools to visualize and analyze the processed signals. The design focused on creating a complete and reliable signal chain while keeping the system modular and easy to test and debug.

Testing & Results

The receiver was tested using five different input signals to evaluate system performance. A 5 Hz sine wave verified basic signal capture, while a 120 Hz sine wave tested higher frequency response. A step input was used to observe transient behavior, and a pulse train tested rapid signal transitions. An amplitude-modulated sine wave confirmed the system could preserve both carrier and envelope information. Overall, the FPGA DSP chain successfully processed each signal while meeting the project’s design requirements and operating constraints.

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