The modern day highly complex computing systems being used in cyber physical systems are built around the System-on-Chip (SoC) devices. These complex SoCs often have multicore processor or microcontroller as central module and various other functional modules such as GPUs, caches, communication subsystems such as DSP, WiFi, cellular network modems, analog, mixed-signal, etc. These systems are used widely in applications such as autonomous vehicles, communication, power transmission, avionics, finance, healthcare, military equipment, etc. Security and reliability of these systems are of utmost importance. Failure of these systems may result in huge financial losses, threat to life, disruption in essential services, etc. Further, a breach in the security of these systems as shown in below Figure, where they are deployed in infrastructure of national importance such as military electronic infrastructure, nuclear facilities, etc., may pose a serious threat to national security. Thus, it is essential for SoC designers to prioritize the development of hardware devices that are resistant to hardware attacks without compromising their testability.
Various Hardware Attacks
In order to ensure reliable in-field operation, the Defect Level (DL) of these systems must be very low. The system DL is directly dependent upon the quality of the SoC chips which is ensured through extensive manufacturing testing of these chips before integrating them into the system. On the other hand, the trustworthiness of these systems is ensured by making these systems resilient to software as well as hardware attacks. To meet the quality requirements (i.e., low DL) of these complex systems, the scan Design-for-Testability (DfT) architecture is deployed in almost every chip for test and diagnosis purposes. Presently, the scan DfT architecture is the only practically viable solution which can provide the required test coverage for modern day complex chips and hence it has become a de-facto industrial test standard. The chip level scan DfT infrastructure is accessed through the board level test/diagnosis standard interface, i.e., IEEE Std. 1149.1 (JTAG). Additionally, in complex System-on-Chips (SoCs) which are the foundation for complex computing systems or cyber-physical systems, IEEE Std. 1500, and IEEE Std. 1687 (IJTAG) are being used to access the SoC cores for test/diagnosis purposes.
An Example of IJTAG Network
Although these standards provide an efficient way to access the on-chip instruments, they have not been designed by taking security aspects into consideration. This test/debug infrastructure provides a side-channel to the attacker for mounting a scan attack on the chip. Any user (authorized/unauthorized) may gain access to the chip internals by exploiting the scan DfT infrastructure and hence steal confidential data such as secret keys, Chip ID, and FPGA firmware, etc.
Thus, the main objective of my research is to develop techniques to make the SoC devices hardware side-channel attack resilient. The countermeasure will be developed by keeping the testability aspects in mind to ensure the required chip reliability. Additionally, the power signature analysis will be tried on the designed scan side-channel secure hardware in order to analyze the vulnerability against the existing power signature analysis attacks.