2025 

• Gaurav Kumar, Mahendra Kumar Gurve, Nitin Nitin, Yamuna Prasad, and Satyadev Ahlawat , “Secure and Scalable Access Protocol for Enhancing IEEE 1687 Network Security,” In SpringerOpen Cybersecurity [accepted] [Q1]

• Pardeep Kumar, Gaurav Kumar, Mahendra Kumar Gurve, Yamuna Prasad, and Satyadev Ahlawat, “On Enhancing the Security of Streaming Scan Network through Dual-Functional TDR,” In ACM Transactions on Design Automation of Electronic Systems (TODAES) [accepted] [Q2]

• Gaurav Kumar, Kushal Pravin Nanote, Sohan Lal, Yamuna Prasad, and Satyadev Ahlawat, “Robust LFSR-based Scrambling to Mitigate Stencil Attack on Main Memory,” In ACM Transactions on Embedded Computing Systems (TECS), vol 24, no. 5s, pp. 1-22, September 2025 [Q2] 

• Anjum Riaz, Gaurav Kumar, Lavi Tyagi, Yamuna Prasad, and Satyadev Ahlawat. “Exploring Non-TAP Interfaces for Efficient and Secure Access to IJTAG Network”. In IEEE Transactions on Device and Materials Reliability (TDMR), vol. 25, no. 1, pp. 76-84, March 2025 [Q2]

2024 

• Anjum Riaz, Gaurav Kumar, Pardeep Kumar, Yamuna Prasad, and Satyadev Ahlawat. “Enhancing the Security of IJTAG network using Inherently Secure SIB”. In VLSI-SoC 2023: Silicon Innovations for Trustworthy Artificial Intelligence. IFIP Advances in Information and Communication Technology, vol 680. Springer, Cham

2025

• Prokash Ghosh, Gaurav Kumar, Sohan Lal, Satyadev Ahlawat, and Virendra Singh, “On Enhancing the Security Against Memory Disclosure Attacks,” in 38th IEEE International System-on-Chip Conference (SOCC), Dubai, UAE, September 29 − October 1, 2025 [accepted]

• Chandranshu Gupta, Gaurav Kumar, Manish Kumar, Satyadev Ahlawat, and Gaurav Varshney. “Poster Abstract: SRAM PUF-Based Logic Locking for Secure Authentication and IP Protection”. In 23rd ACM Conference on Embedded Networked Sensor Systems, SenSys 2025, Irvine, USA, May 6-9, 2025 [poster]

• Mahendra Kumar Gurve, Gaurav Kumar, Anuj Kumar, Yamuna Prasad, and Satyadev Ahlawat. “Approximating Nonlinear Activation Function Using Genetic Programming”. In 58th International Symposium on Circuits and Systems Conference, ISCAS 2025, London, UK, May 25-28, 2025 [ppt]

• Anjum Riaz, Gaurav Kumar, Yamuna Prasad, Satyadev Ahlawat and Virendra Singh. “A New Hardware Trojan Attack on Scan-Obfuscated Logic-Locked Circuits”. In 58th International Symposium on Circuits and Systems Conference, ISCAS 2025, London, UK, May 25-28, 2025 [ppt]

• Gaurav Kumar, Shaik Ashfaq Hussain, Anjum Riaz, Yamuna Prasad, and Satyadev Ahlawat. “Compatibility Graph Assisted Automatic Hardware Trojan Insertion Framework”. In 28th Design Automation and Test in Europe Conference, DATE 2025, Lyon, France, March 31- April 2, 2025 [ppt] 

2024

• Gaurav Kumar, and Satyadev Ahlawat. “Securing the System-on-Chip Against Side-channel Attacks”. In PhD Forum of 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, USA, June 23-27, 2024 [poster]

• Gaurav Kumar, Anjum Riaz, Pardeep Kumar, Yamuna Prasad, and Satyadev Ahlawat. “On Evaluating Test Response Obfuscation and Encryption Countermeasures”. In 30th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2024, Rennes, Brittany, France, July 3-5, 2024 [poster]

• Mahendra Kumar Gurve, Gaurav Kumar, Sankar Behera, Yamuna Prasad,  and Satyadev Ahlawat. “On Exploring Non-negative Matrix Factorization for Deep Neural Network Compression”.  In 21st International SoC Design Conference, ISOCC 2024, Sapporo, Hokkaido, Japan, August 19-22, 2024 [ppt]

2023

• Gaurav Kumar, Anjum Riaz, Yamuna Prasad, and Satyadev Ahlawat. “On Enhancing the Security of Streaming Scan Network Architecture”.  In 32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023 [ppt]

• Anjum Riaz, Gaurav Kumar, Pardeep Kumar, Yamuna Prasad, and Satyadev Ahlawat. “On Protecting IJTAG using an Inherently Secure SIB”. In 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Sharjah, UAE, October 16- 18, 2023 [ppt]

• Gaurav Kumar, Anjum Riaz, Yamuna Prasad, and Satyadev Ahlawat. “On Evaluating the Security of Dynamic Scan Obfuscation Scheme”. In 29th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2023, Chania, Greece, July 3-5, 2023 [ppt]

2022

• Gaurav Kumar, Anjum Riaz, Yamuna Prasad, and Satyadev Ahlawat. “A New Access Protocol for Elevating the Security of IJTAG Network”. In 31st IEEE Asian Test Symposium, ATS 2022, Taichung, Taiwan, November 21-24, 2022 [ppt]

• Gaurav Kumar, Anjum Riaz, Yamuna Prasad, and Satyadev Ahlawat. “Power Analysis Attack on Locking SIB based IJTAG Architecture”. In 30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022 [ppt]

• Gaurav Kumar, Anjum Riaz, Yamuna Prasad, and Satyadev Ahlawat. “On Attacking IJTAG Architecture based on Locking SIB with Security LFSR”. In 28th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2022, Torino, Italy, September 12-14, 2022 [ppt]

• Gaurav Kumar, Anuj Kumar, Satyadev Ahlawat, and Yamuna Prasad. “Low Cost Implementation of Deep Neural Network On Hardware”. In 26th International Symposium on VLSI Design and Test, VDAT 2022, Jammu, India, July 17-19, 2022 [ppt]

• Anjum Riaz, Gaurav Kumar, Jaynarayan Tudu, and Satyadev Ahlawat. “On Protecting IJTAG from Data Sniffing and Alteration Attacks”. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Pafos, Cyprus, July 4-6, 2022 [ppt]

• Gaurav Kumar, Anjum Riaz, Yamuna Prasad, and Satyadev Ahlawat. “On Attacking Locking SIB Based IJTAG Architecture”. In 32nd Proceedings of the Great Lakes Symposium on VLSI 2022, GLSVLSI  2022, page 105–109, New York, NY, USA, June 6-8, 2022 [ppt]