Gaurav Narang, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Krishnendu Chakrabarty, and Partha Pratim Pande. 2025. GINA: Exploiting Graph Neural Network Layer Features for Energy Efficient Inferencing in NVM-based PIM Accelerators. ACM Trans. Embed. Comput. Syst. 24, 5s, Article 116 (November 2025), 26 pages. https://doi.org/10.1145/3759918
Ogbogu, C., Narang, G., Joardar, B.K., Doppa, J.R., Chakrabarty, K. and Pande, P.P., 2025. HePGA: A Heterogeneous Processing-in-Memory based GNN Training Accelerator. arXiv preprint arXiv:2508.16011.
Narang, G, Doppa, JR, & Pande, PP (2025). Odin: Learning to Optimize Operation Unit Configuration for Energy-efficient DNN Inferencing. 2025 Design, Automation &Test in Europe Conference (DATE), 1-7
Narang, G, Ogbogu, C, Doppa, JR, & Pande, PP (2024). TEFLON: Thermally efficient dataflow-aware 3D NoC for accelerating CNN inferencing on manycore PIM architectures. ACM Transactions on Embedded Computing Systems, 23(5), 1-23
Ogbogu, C, Narang, G, Joardar, BK, Doppa, JR, Chakrabarty, K, & Pande, PP (2024). HuNT: Exploiting heterogeneous PIM devices to design a 3-D manycore architecture for DNN training. IEEE Transactions on Computer-Aided Design of Integrated Circuits and …
Sharma, H, Narang, G, Doppa, JR, Ogras, U, & Pande, PP (2024). Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads. 2024 Design, Automation &Test in Europe Conference &Exhibition (DATE), 1-6
Narang, G, Doppa, JR, & Pande, PP (2024). Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ogbogu, C, Narang, G, Joardar, BK, Doppa, JR, & Pande, PP (2024). Heterogeneous Manycore In-Memory Computing Architectures. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided …
Narang, G, Deshwal, A, Ayoub, R, Kishinevsky, M, Doppa, J Rao, & Pande, PP (2023). Dynamic power management in large manycore systems: A learning-to-search framework. ACM Transactions on Design Automation of Electronic Systems, 28(5), 1-21
Narang, G, Ayoub, R, Kishinevsky, M, Doppa, JR, & Pande, PP (2023). Uncertainty-aware online learning for dynamic power management in large manycore systems. 2023 IEEE/ACM International Symposium on Low Power Electronics and Design …
Gupta, PR, Visweswaran, GS, Narang, G, & Grover, A (2016). Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. 2016 29th IEEE International System-on-Chip Conference (SOCC), 290-295
Narang, G, Sharma, P, Jain, M, & Grover, A (2015). Statistical analysis of 64mb sram for optimizing yield and write performance. 2015 28th International Conference on VLSI Design, 411-416
Narang, G, Fell, A, Gupta, PR, & Grover, A (2015). Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems. 2015 28th IEEE International System-on-Chip Conference (SOCC), 105-110