Publication

2022

Super-Nernstian Isfet Combining Two-Dimensional WSe2/MoS2 Heterostructure with Negative Capacitance

Sooraj Sanjay, Fahimul Islam Sakib, Mainul Hossain and Navakanta Bhat

ECS Meeting Abstracts, Volume MA2022-02, D01: Semiconductors, Dielectrics, and Metals for Nanoelectronics 19

Background

Ion-sensitive field-effect transistors (ISFETs) are quite popular as compact, low-cost biosensors with fast response time and label-free detection1. They can be used as pH sensors or functionalized for complex biomolecule detection. The voltage sensitivity (Sv) in classical ISFETs is fundamentally limited to 59 mV/pH (Nernst limit). Surpassing the Nernst limit requires complex device architectures or novel transport phenomena. Sensitivity beyond the Nernst limit can be achieved using specific device architectures such as dual gate ISFETs2, negative capacitance ISFETs (NC-ISFET)3, tunnel ISFETs4, etc. Compatible architectures can be combined for further enhancements in sensitivity.

First, we experimentally demonstrate a super-Nernstian hetero-ISFET that uses 2-D WSe2/MoS2 heterostructure in a double-gated configuration5. The schematic of the device structure is shown in Fig. 1(a) along with its dimensions. The fluid gate to the pH solution is biased at VFG = 0 V and the voltage sensitivity (SV) is extracted by applying bias to the back-gate (VBG). Fig. 1(b) shows the variation of drain current for change in VBG at different pH. The voltage sensitivity is also included in the same graph. The device uses charge screening due to the interface traps and inversion charges at the hetero-interface to modulate the back-gate transconductance (gmb), thereby allowing super sensitivity.

2021

Negative Capacitance Gate-All-Around Tunnel FETs for Highly Sensitive Label-Free Biosensors

F. I. Sakib, Md. Azizul Hasan, and M. Hossain

IEEE Trans. Electron. Devices, vol. 69, pp. 311-317, 2021 [Impact Factor: 2.913; SJR: Q1, JCR: Q2]

Background

We propose a nanoscale, highly sensitive and label-free biosensor based on negative capacitance gateall-around tunnel field-effect transistor (NC-GAA-TFET). NC-GAA-TFETs provide steeper, sub-60 mV/dec subthreshold swing (SS) and higher drive current compared with the conventional gate-all-around tunnel field-effect transistor (GAA-TFETs). The combination of differential voltage amplification, due to the negative capacitance (NC) of the gate ferroelectric, and the quantum mechanical band-toband tunneling (BTBT) effect leads to a significant boost in current sensitivity (SI) compared with the state-of-theart field-effect transistor (FET)-based sensing devices. 1-D Landau–Khalatnikov (L-K) equations are solved numerically and integrated with 3-D technology computer-aided design (TCAD) simulations to evaluate the sensor performance. The results show that the proposed sensor can achieve SS down to 27 mV/dec. The subthermal SS can be maintained over five decades of current leading to reduced power consumption in the weak inversion region and achieving SI as high as ∼10^6 and ∼10^5 for detecting biomolecules and pH changes, respectively. In addition, NC-GAA-TFETs provide ∼7× higher signal-to-noise ratio (SNR) than their baseline counterparts which make NC-GAA-TFETs promising candidates for low noise and ultrasensitive biosensing platforms.

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

F. I. Sakib, Md. Azizul Hasan, and M. Hossain

Engineering Research Express, IOP, vol. 3, 045044, 2021 [Impact Factor: N/A; SJR: N/A; JCR: N/A].

Background

Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (ION) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher ION/IOFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

Performance Comparison of Negative Capacitance in Si Nanowire and Nanosheet Field Effect Transistors

Md. Azizul Hasan, F. I. Sakib and M. Hossain

2021 Virtual MRS Spring Meeting and Exhibit-Symposium EL09-Ferroelectricity and Negative Capacitance—Fundamentals, Applications and Controversies, Seattle, WA, USA, (2021).

Background

The superior electrostatic control and high scalability of nanowire (NW) and nanosheet (NS) gate-all-around field-effect-transistors (FETs) make them promising alternatives to FinFETs in advanced technology nodes. Negative capacitance (NC) effect, originating from a ferroelectric (FE) material in the gate stack, can provide an elegant solution for the much-needed voltage scaling in these aggressively scaled devices. In this work, a comparative analysis on the performance of NC-NWFETs and NC-NSFETs is presented through fully calibrated, three-dimensional TCAD simulations. For the same layout footprint (LF), both single channel NC-NSFETs and those, with vertically stacked NSs, have been considered. Single channel NC-NSFET exhibits 9% lower subthreshold swing (SS) and 35% higher ON-current (ION) than NC-NWFET of comparable device dimensions. In contrast to NC-NWFET, capacitance matching between the FE and the underlying metal-oxide-semiconductor (MOS) capacitance is achieved with a thinner FE layer in NC-NSFET. This is particularly significant, since a thinner FE layer enables further scaling of these NC devices. In addition, NC-NSFET, with vertically stacked NSs, can achieve 4× higher ION and ~50% lower SS than NC-NWFET, owing to higher effective width and better capacitance matching. A high ION/IOFF ratio of 10^6, with low operating voltage (VDD = 0.2V), is obtained for the NC-NSFET. The significantly higher ION in NC-NSFET also results in faster switching, with significantly lower power consumption, at VDD < 0.3 V. The performance of stacked NC-NSFETs can be optimized by tuning the width and thickness of the NSs. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths (LG) as small as 10 nm

2020

Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors

F. I. Sakib, Md. Azizul Hasan and M. Hossain

IEEE Trans. Electron. Devices, vol. 67, pp. 5236-5242, 2020. [Impact Factor: 2.913; SJR: Q1, JCR: Q2]

Background

A comprehensive study on the performance of NC-NSFETs has been presented, using fully calibrated 3-D TCAD simulations. SS in single channel NC-NSFETs are found to be ∼9% and ∼38% lower than NC-NWFET and NC-FinFET, respectively, for comparable device dimensions. Capacitance matching, between FE and MOS capacitances, enables hysteresis free operation with a thinner FE, enabling ultrascaling of NC-NSFETs. Single stack NC-NSFETs exhibit higher Ion and lower SS than the double stack and offer faster switching characteristics at low VDD. DIBR (N-DIBL), with associated NDR behavior, has been studied with varying LG for single stack NC-NSFETs. Key device design parameters like TNS, WNS, and metal WF variations have also been explored. Nonuniformity in NS dimensions, within a given stack, arising from process variations, also influences device behavior. Superior performance can be achieved with thinner NSs while the width needs to be tuned according to the design specifications. Moreover, significant improvement in terms of leakage current and Ion/Ioff ratio can be attained by tuning the metal WF. The results presented here can be useful for performance optimization of NC-NSFETs, scalable to the 5-nm device node and beyond.

2019

Influence of device architecture on the performance of negative capacitance MFMIS transistors

F. I. Sakib, F. E. Mullick, S. Shahnewaz, S. Islam, and M. Hossain

Semicond. Sci. Technol., vol. 35, 025005, 2019. [Impact Factor: 2.352; SJR: Q1; JCR: Q2].

Background

We report a comparative analysis of the performance of negative capacitance field effect transistors (NCFETs) with single gate, double gate, tri-gate (FinFET) and gate-all-around (GAA) device architectures, using TCAD simulations. Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is chosen for all NCFET devices. The NC behavior is attributed to the ferroelectric (FE) layer introduced into the gate stack of these devices. With aluminum doped hafnium oxide as the FE, electrical characteristics of NCFETs, with 40 nm or equivalent gate length, were simulated by solving a combination of Landau-Khalatnikov (LK) equation and metal oxide semiconductor field effect transistor (MOSFET) equations. At a drain voltage, VD= 50 mV, NC-FinFET and NC-GAAFET achieve 45% and 67.5% reduction in subthreshold swing (SS), respectively, compared to baseline devices, without any NC effect. In addition to improving sub-threshold performance, NCFETs have also shown higher ION/IOFF ratio than baseline devices for all device architectures. By tuning the thickness of the FE material, we have demonstrated capacitance matching, between FE and MOS capacitances, for non-hysteretic operation in NC-FinFET and NC-GAAFET. Matching FE and MOS capacitances allow for maximum NC effect. Results obtained from our TCAD simulations are consistent with reported experimental data and could provide useful insights into the design, operation and performance improvement of next generation NCFET devices