Embedded Files
- Chun-Da Tu, Shu-Wei Tsao, Cheng-Han Huang, Wei-Shan Yu, Yung-Chih Chen, Ming-Hsien Lee, Kai-Wei Hong, Hsing-Sheng Chang, Shu-Ching Lee, Chung-Hong Kuo, “A Gate Driver Circuit with a-IGZO TFTs for 8-inch QXGA TFT-LCD Panel,” in the Society for Information Display, Volume 48, Issue 1, May 2017.
- Chun-Da Tu, Yung-Chin Chen, Cheng-Han Huang, Kai-Wei Hong, Hsiang-Sheng Chang, Chung-Hong Kuo, “A Narrow Gate Driver Circuit with a-Si TFTs for 8” WQXGA TFT-LCD Panel,” in the Society for Information Display, Volume 46, Issue 1, July 2015.
- Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu and Chien-Cheng Chen, “Loading Effect Insensitive and High Precision Clock Synchronization Circuit,” in Proc. IEEE European Solid-State Circuits Conference, Sep. 2010, pp. 514 – 517.
- Wei-Chang Liu(1), Chih-Hsien Lin(1), Shyh-Jye Jou(1), Hung-Wen Lu(2), Chau-Chin Su(2), Kai-Wei Hong(3), Kuo-Hsing Cheng(3), Shyue-Wen Yang(4) and Ming-Hwa Sheu(4), “A Micro-Network on Chip with 10-Gb/s Transmission Link” in Proc. IEEE Asian Solid-State Circuits Conference, Taipei, 2009.
- Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, and Yen-Hsueh Wu,, “A Low Jitter Self-Calibration PLL for 10Gbps SoC Transmission Links Application,” IEEE International Conference on Electronics, Circuits and Systems, pp.786 - 789 , Aug. 2008.
- Kuo-Hsing Cheng, Kai-Wei Hung, Chien-Hsien Lee and Chen-Lung Wu, “A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay,” IEEE International Conference on Electronics, Circuits and Systems, pp.569-572, Dec. 2006.
- Chia-Chun Tsai, Kai-Wei Hong, Yuh-Shyan Hwang, Wen-Ta Lee, and Trong-Yen Lee, “New Power Saving Design Method for CMOS Flash ADC,” The IEEE 47th International Midwest Symposium on Circuits and Systems, pp. III-371-III-374, July 2004.
- Kuo-Hsing Cheng, Chi-Fa Hsu, and Kai-Wei Hong, “An All-Digital Output Load Insensitive High Resolution Clock Synchronization Buffer with Flexible Duty Cycle,” the 21th VLSI Design/CAD Symposium, Aug. 2010, pp. 315 – 318.
- Kuo-Hsing Cheng, Chi-Hsiang Chen, Kai-Wei Hong, Jen-Chieh Liu and Sing-Shan Ko” A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,” the 20th VLSI Design/CAD Symposium, Aug. 2009.
- Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong ” A Low Jitter 2.5-GHz Self-Calibration PLL,” the 18th VLSI Design/CAD Symposium, Aug. 2007.
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