期刊論文

Zhen-Jie Hong, Yu-Lung Lo, Kuan-Yu Shen, Guan-Yu Chen and Wei-Ju Li, "A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display," Analog Integrated Circuits and Signal Processing, Nov., 2023, https://doi.org/10.1007/s10470-023-02192-6.

Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, and Bo-Qian Jiang ,“An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , vol. 20 , no. 10 , pp. 1818-1827 , Oct. 2012 ( SCI, EI, IF:1.698 ) 

Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, and Jen-Chieh Liu, “A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 19 , no. 7 , pp. 1218-1228 , Jul. 2011 (SCI, EI, IF:1.698 ). 

Kuo-Hsing Cheng, Kai-Wei Hong, Yu-Lung Lo, Chen-Lung Wu and Chien-Hsien Lee, “A Dynamic Frequency Tracking and Phase Error Compensation Clock De-skew Buffer,” IEE Electronics Letters , vol. 46 , no. 25 , pp. 1653-1655 , Dec. 2010 (SCI, EI, IF:1.155).

 Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang and Kai-Wei Hong, “A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, , pp. 1325-1335 , Jun. 2010 (SCI, EI, IF:1.698).

 Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong and Chin-Cheng Kuo: A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Transactions 92-C(7), pp. 964-972, 2009 (SCI, EI, IF:0.827 ).

Chia-Chun Tsai, Kai-Wei Hong, and Trong-Yen Lee, “A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital Converters,” JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 18, No. 5, pp. 933-945, 2009 (SCI, EI, IF: 0.481).