2025

[69] Sanghyeon Choi, Sai Sukruth Bezugam, Tinish Bhattacharya, Dongseok Kwon, Dmitri B Strukov, "Wafer-scale fabrication of memristive passive crossbar circuits for brain-scale neuromorphic computing," Nature Communications, 2025

[68] Jinsu Kim, Hansol Kim, Jisung Im, Sung-Tae Lee, Dongseok Kwon, Nagyong Choi, Sung Yun Woo, "Comparative Analysis of Grain Boundary Effects in FET-Type and Diode-Type 3-D NAND Flash Memory, " IEEE Transactions on Electron Devices, 2025.

[67] G. Pedretti, F. Bohm, T. Bhattacharya, Arne Heittmann, Xiangyi Zhang, Mohammad Hizzani, George Hutchinson, Dongseok Kwon, John Moon, Elisabetta Valiante, Ignacio Rozada, Catherine E Graves, Jim Ignowski, Masoud Mohseni, John Paul Strachan, Dmitri Strukov, Ray Beausoleil, Thomas Van Vaerenbergh, "Solving Boolean satisfiability problems with resistive content addressable memories," npj Unconventional Computing, 2025.

2024

[66] W. Shin, R.-H. Koo, S. Kim, D. Kwon, J.-J. Kim, D. Kwon, J.-H. Lee, "Robust 1/f Noise Unaffected by Program/Erase Cycling-Induced Damage in Ferroelectric Schottky Barrier FETs," IEEE Electron Device Letters, 2024.

[65] R.-H. Koo, W. Shi, G. Jung, D. Kwon, J.-J. Kim, D. Kwon, and J.-H. Lee, "Stochasticity in ferroelectric memory devices with different bottom electrode crystallinity," Chaos, Solitons & Fractals, 2024.

[64] J. Kim, J. Im, W. Shin, S. Lee, S. Oh, D. Kwon, G. Jung, W. Y. Choi, and J.-H. Lee, "Demonstration of In-Memory Biosignal Analysis: Novel High-Density and Low-Power 3D Flash Memory Array for Arrhythmia Detection," Advanced Science, 2024.

[63] S.-H. Park, J. Ko, I.-S. Lee, R.-H. Koo, J.-H. Kim, Y. Yang, D. Kwon, J.-J. Kim, and J.-H. Lee, "On-Chip Learning in Vertical NAND Flash Memory Using Forward-Forward Algorithm,", IEEE Transcations on Electron Devices, 2024.

[62] J. Hwang, M.-K. Park, W.-M. Kang, R.-H. Koo, K.-H. Lee, D. Kwon, W. Y. Choi, J.-H. Lee,"NOR-type Flash Array Based on Four-terminal TFT Synaptic Devices Capable of Selective Program/Erase Exploiting Fowler-Nordheim Tunneling," IEEE Electron Device Letters, 2024.

[61] J. Kim, W. Shin, J. Yim, D. Kwon, D. Kwon, and J.-H. Lee, "Toward Optimized In-Memory Reinforcement Learning: Leveraging 1/f Noise of Synaptic Ferroelectric Field-Effect-Transistors for Efficient Exploration," Advanced Intelligent Systems, 2024.

[60] D. Kwon, S. Y. Woo, J. Hwang, H. Kim, J.-H. Bae, W. Shin, B.-G. Park, and J.-H. Lee, “Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory,” IEEE Transactions on Neural Networks and Learning Systems, Accepted.

[59] D. Kwon*, J.-H. Ko*, J. Hwang, K.-H. Lee, S. Oh, J. Kim, J. Im, R.-H. Koo, J.-J. Kim, and J.-H. Lee, “SNNSim: Investigation and Optimization of Large-Scale Analog Spiking Neural Networks Based on Flash Memory Devices,” Advanced Intelligent Systems, 2024. (Co-First Author)

[58] D. Kwon*, K.-H. Lee*, I.-S. Lee, J. Hwang, J. Im, J.-H. Bae, W.-Y. Choi, S. Y. Woo, and J.-H. Lee, “Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardwrae Neural Networks,” Advanced Intelligent Systems, 2024. (Co-First Author)

2023

[57] R.-H. Koo, W. Shin, S. Kim, J. Im, S.-H. Park, J.-H. Ko, D. Kwon, J.-J. Kim, D. Kwon, and J.-H. Lee, “Proposition of Adaptive Read Bias: A Solution to Overcome Power and Scaling Limitations in Ferroelectric-Based Neuromorphic System,” Advanced Science, 2023

[56] D. Kwon*, E.-C. Park, W. Shin, R.-H. Koo, J. Hwang, J.-H. Bae, D. Kwon, and J.-H. Lee, “Analog Synaptic Devices Based on IGZO Thin-Film Transistors with a Metal-Ferroelectric-Metal-Insulator-Semiconductor Structure for High-Performance Neuromorphic Systems,” Advanced Intelligent Systems, 2023. 

[55] G. Yeom, D. Kwon, W. Shin, M.-K. Park, J.-J. Kim, and J.-H. Lee, “Fast-response/recovery In2O3 thin-film transistor-type NO2 gas sensor with floating-gate at low temperature,” Sensors and Actuators B: Chemical, 2023.

[54] S.-H. Park, H.-N. Yoo, Y. Yang, J.-W. Back, R.-H. Koo, D. Kwon, J.-J. Kim, and J.-H. Lee, “Voltage scheme for string-select transistors to improve inhibition characteristics during 1-bit erase in vertical NAND flash,” Applied Physics Letters, 2023.

[53] G. Jung, J. Kim, S. Hong, H. Shin, Y. Jeong, W. Shin, D. Kwon, W.-Y. Choi, and J.-H. Lee, “Energy efficient artificial olfactory system with integrated sensing and computing capabilities for food spoilage detection,” Advanced Science, 2023.

[52] R.-H. Koo, W. Shin, S. Ryu, K. Lee, S.-H. Park, J. Im, J.-H. Ko, J.-H. Kim, D. Kwon, J.-J. Kim, D. Kwon, and J.-H. Lee, “Comparative Analysis of n- and p-type Ferroelectric Tunnel Junctions Through Understanding of non-FE Resistance Switching,” IEEE Electron Device Letters, 2023.

[51] W. Shin, S. Kim, R.-H. Koo, D. Kwon, J.-J. Kim, D.-H. Kwon, D. Kwon, J.-H. Lee, “Channel-Length-Dependent Low-Frequency Noise Characteristics of Ferroelectric Junctionless Poly-Si Thin-Film Transistors,” IEEE Electron Device Letters, 2023.

[50] D. Kwon, S. Y. Woo, K.-H. Lee, J. Hwang, H. Kim, S.-H. Park, W. Shin, J.-H. Bae, J.-J. Kim, and J.-H. Lee, “Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons,” Science Advances, vol. 9, no. 29, 2023. (IF: 13.6)

[49] D. Kwon, M.-K. Park, W.-M. Kang, J. Hwang, R.-H. Koo, J.-H. Bae, and J.-H. Lee, “Hardware-Based Ternary Neural Network Using AND-Type Poly-Si TFT Array and Its Optimization Guideline,” IEEE Transactions on Electron Devices, 2023.

[48] W. Shin, S. Kim, R.-H. Koo, D. Kwon, J.-J. Kim, D.-H. Kwon, D. Kwon, and J.-H. Lee, “Optimizing Post-Metal Annealing Temperature Considering Different Resistive Switching Mechanisms in Ferroelectric Tunnel Junction,” IEEE Electron Device Letters, 2023.

[47] W. Shin, E. C. Park, R.-H. Koo, D. Kwon, D. Kwon, and J.-H. Lee, “Low-frequency noise characteristics of indium-gallium-zinc oxide ferroelectric thin-film transistors with metal-ferroelectric-metal-insulator-semiconductor structure,” Applied Physics Letters, 2023.

[46] W. Shin, R.-H. Koo, K.-K. Min, B. Kwang, D. Kwon, D. Kwon, and J.-H. Lee, “Effects of temperature and DC cycling stress on resistive switching mechanisms in hafnia-based ferroelectric tunnel junction,” Applied Physics Letters, 2023.

[45] D. Kwon, H. Kim, K.-H. Lee, J. Hwang, W. Shin, J.-H. Bae, S. Y. Woo, and J.-H. Lee, “Super-steep synapses based on positive feedback devices for reliable binary neural networks,” Applied Physics Letters, 122, 102101, 2023.

[44] W. Shin, J. Im, R.-H. Koo, J. Kim, D. Kwon, J.-J. Kim, D. Kwon, and J.-H. Lee, “Self-Curable Synaptic Ferroelectric FET Arrays for Neuromorphic Convolutional Neural Network,” Advanced Science, 2023.

[43] W. Shin, K.-K. Min, J.-H. Bae, J. Kim, R.-H. Koo, D. Kwon, J.-J. Kim, D. Kwon, and J.-H. Lee, “1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Networks,” Advanced Intelligent Systems, 2023.

2022

[42] W. Shin, R.-H. Koo, K. K. Min, D. Kwon, J.-J. Kim, D. Kwon, J.-H. Lee, “Unveiling Resistance Switching Mechanisms in Undoped HfOx Ferroelectric Tunnel Junction Using Low-Frequency Noise Spectroscopy,” IEEE Electron Device Letters, 2022.

[41] S. Y. Woo, W.-M. Kang, Y.-T. Seo, S. Lee, D. Kwon, S. Oh, Jong-Ho Bae, J.-H. Lee, “Demonstration of integrate-and-fire neuron circuit for spiking neural networks,” Solid-State Electronics, vol. 198, 2022.

[40] S. Y. Woo, D. Kwon, B.-G. Park, J.-H. Lee, and J.-H. Bae, “Demonstration of Pulse Width Modulation Function Using Single Positive Feedback Device for Neuron,” IEEE Electron Device Letters, vol. 44, no. 1, 2022.

[39] R.-H. Koo, W. Shin, K. K. Min, D. Kwon, D. H. Kim, J.-J. Kim, D. Kwon, and J.-H. Lee, “Effect of Carrier Transport Process on Tunneling Electroresistance in Ferroelectric Tunnel Junction,” IEEE Electron Device Letters, 2022.

[38] D. Kwon*, K.-H. Lee, S. Y. Woo, J. H. Ko, W. Y. Choi, B.-G. Park, and J.-H. Lee, “Highly Linear Analog Spike Processing Block Integrated with an AND-Type Flash Array and CMOS Neuron Circuits,” IEEE Transactions on Electron Devices, vol. 69, no. 11, 2022. (Co-First Author)

[37] W. Shin, R.-H. Koo, S. Hong, D. Kwon, J. Hwang, B.-G. Park, and J.-H. Lee, “Highly Efficient Self-Curing Method in MOSFET Using Parasitic Bipolar Junction Transistor,” IEEE Electron Device Letters, vol. 43, no. 7, 2022.

[36] S.-T. Lee, H. Kim, H. Yoo, D. Kwon, and J.-H. Lee, “Novel, parallel and differential synaptic architecture based on NAND flash memory for high-density and highly-reliable binary neural networks,” Neurocomputing, vol. 498, no. 7, 2022.

[35] W. Shin, J.-H. Bae, D. Kwon, R.-H. Koo, B.-G. Park, D. Kwon, and J.-H. Lee, “Investigation of Low-Frequency Noise Characteristics of Ferroelectric Tunnel Junction: from Conduction Mechanism and Scaling Perspectives,” IEEE Electron Device Letters, vol. 43, no. 6, 2022.

[34] D. Kwon, S. Y. Woo, and J.-H. Lee, “Review of Analog Neuron Devices for Hardware-based Spiking Neural Networks,” Journal of Semiconductor Technology and Science, vol. 22, no. 2, 2022.

[33] J. Im, J. Kim, H. Yoo, J.-W. Baek, D. Kwon, S. Oh, J. Kim, J. Hwang, B.-G. Park, and J.-H. Lee, “On-Chip Trainable Spiking Neural Networks Using Time-To-First-Spike Encoding,” IEEE Access, vol. 10, 2022.

[32] S. Oh, D. Kwon, G. Yeom, W.-M. Kang, S. Lee, S. Y. Woo, J. Kim, J.-H. Lee, “Neuron Circuits for Low-Power Spiking Neural Networks Using Time-To-First-Spike Encoding,” IEEE Access, vol. 10, 2022.

[31] W. Shin, K.-K. Min, J.-H. Bae, J.-K. Lee, S. Hong, J. Kim, Y. Jeong, D. Kwon, R.-H. Koo, G. Jung, C. Han, J. Kim, B.-G. Park, D. Kwon, and J.-H. Lee, “Synergistic improvement of sensing performance in ferroelectric transistor gas sensors using remnant polarization,” Materials Horizons, vol. 9, 2022.

[30] W. Shin, K.-K. Min, J.-H. Bae, J. Yim, D. Kwon, Y. Kim, J. Yu, J. Hwang, B.-G. Park, D. Kwon, and J.-H. Lee, “Comprehensive and accurate analysis of the working principle in ferroelectric tunnel junctions using low-frequency noise spectroscopy,” Nanoscale, vol. 14, no. 6, 2022.

2021

[29] M.-K. Park, H.-N. Yoo, J. Hwang, S. Y. Woo, D. Kwon, Y.-T. Seo, J.-H. Lee, and J.-H. Bae, “CMOS-Compatible Low-Power Gated Diode Synaptic Device for Hardware-Based Neural Network,” IEEE Transactions on Electron Devices, vol. 69, no. 2, 2021.

[28] W. Shin, J.-H. Bae, S. Kim, K. Lee, D. Kwon, B.-G. Park, and D. Kwon, and J.-H. Lee, “Effects of high-pressure annealing on the low-frequency noise characteristics in ferroelectric FET,” IEEE Electron Device Letters, vol. 43, no. 1, 2021.

[27] D. Kwon, G. Jung, W. Shin, Y. Jeong, S. Hong, S. Oh, J. Kim, J.-H. Bae, B.-G. Park, and J.-H. Lee, “Efficient fusion of spiking neural networks and FET-type gas sensors for a fast and reliable artificial olfactory system,” Sensors and Actuators B: Chemical, vol. 345, 130419, 2021. (JCR ranking 1st)

[26] D. Kwon, S. Y. Woo, J.-H. Bae, S. Lim, B.-G. Park, and J.-H. Lee, “Hardware-Based Spiking Neural Networks Using Capacitor-Less Positive Feedback Neuron Devices,” IEEE Transactions on Electron Devices, vol. 68, no. 9, 2021.

[25] H. Kim, J. Hwang, D. Kwon, J. Kim, M.-K. Park, J. Im, B.-G. Park, and J.-H. Lee, “Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks,” Advanced Intelligent Systems, vol. 3, no. 8, 2100064, 2021.

[24] J. Kim, D. Kwon, S. Y. Woo, W.-M. Kang, S. Lee, S. Oh, C.-H. Kim, J.-H. Bae, B.-G. Park, J.-H. Lee, “On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm,” Neural Computing and Applications, vol. 33, no. 15, 2021.

[23] D. Kwon, G. Jung, W. Shin, Y. Jeong, S. Hong, S. Oh, J.-H. Bae, B.-G. Park, and J.-H. Lee, “Low-power and reliable gas sensing system based on recurrent neural networks,” Sensors and Actuators B: Chemical, vol. 340, 129258, 2021. (JCR ranking 1st)

[22] D. Kwon*, Y.-T. Seo, Y. Noh, S. Lee, M.-K. Park, S. Y. Woo, B.-G. Park, and J.-H. Lee, “3-D AND-Type Flash Memory Architecture With High-k Gate Dielectric for High-Density Synaptic Devices,” IEEE Transactions on Electron Device, vol. 68, no. 8, 2021. (Co-First Author)

[21] S. Oh, S. Lee, S. Y. Woo, D. Kwon, J. Im, J. Hwang, J.-H. Bae, B.-G. Park, and J.-H. Lee, “Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model,” IEEE Access, vol. 9, 2021.

[20] D. Kwon*, W.-M. Kang, S. Y. Woo, S. Lee, H. Yoo, J. Kim, B.-G. Park, and J.-H. Lee, “Hardware-based spiking neural networks using a TFT-type AND flash memory array architecture based on direct feedback alignment,” IEEE Access, vol. 9, 2021. (Co-First Author)

[19] D. Kwon*, W. Shin, J.-H. Bae, S. Lim, B.-G. Park, and J.-H. Lee, “Impacts of Program/Erase Cycling on the Low-Frequency Noise Characteristics of Reconfigurable Gated Schottky Diodes,” IEEE Electron Device Letters, vol. 42, no. 6. 2021. (Co-First Author)

[18] J. Kim, D. Kwon, S. Y. Woo, W.-M. Kang, S. Lee, S. Oh, C.-H. Kim, J.-H. Bae, B.-G. Park, and J.-H. Lee, “Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality,” Neurocomputing, vol. 428, 2021.

[17] D. Kwon, W. Shin, J.-H. Bae, S. Lim, B.-G. Park, and J.-H. Lee, “Investigation of low-frequency noise characteristics in gated Schottky diodes,” IEEE Electron Device Letters, vol. 42, no. 3, 2021.

2020

[16] D. Kwon*, S. Y. Woo*, N. Choi, W.-M. Kang, Y.-T. Seo, M.-K. Park, J.-H. Bae, B.-G. Park, and J.-H. Lee, “Low-power and high-density neuron device for simultaneous processing of excitatory and inhibitory signals in neuromorphic systems,” IEEE Access, vol. 8, 2020. (Co-First Author)

[15] S.-T. Lee, S. Lim, J.-H. Bae, D. Kwon, H. Kim, B.-G. Park, and J.-H. Lee, “Pruning for hardware-based deep spiking neural networks using gated Schottky diode as synaptic devices,” Journal of Nanoscience and Nanotechnology, vol. 20, no. 11, 2020.

[14] S.-T. Lee, S. Lim, N. Choi, J.-H. Bae, D. Kwon, H. Kim, B.-G. Park, and J.-H. Lee, “Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND Flash Cells,” Journal of Nanoscience and Nanotechnology, vol. 20, no. 7, 2020.

[13] S.-T. Lee, D. Kwon, H. Kim, H. Yoo, and J.-H. Lee, “NAND flash based novel synaptic architecture for highly robust and high-density quantized neural networks with binary neuron activation of (1, 0),” IEEE Access, vol. 8, 2020.

[12] H. Kim, J.-H. Bae, S. Lim, S.-T. Lee, Y.-T. Seo, D. Kwon, B.-G. Park, and J.-H. Lee, “Efficient precise weight tuning protocol considering variation of the synaptic devices and target accuracy,” Neurocomputing, vol. 378, 2020.

[11] W. Shin, G. Jung, S. Hong, Y. Jeong, J. Park, D. Kim, D. Jang, D. Kwon, J.-H. Bae, B.-G. Park, and J.-H. Lee, “Proposition of deposition and bias conditions for optimal signal-to-noise-ratio in resistor- and FET-type gas sensors,” Nanoscale, vol. 12, no. 8, 2020.

[10] D. Kwon*, S. Lim, J.-H. Bae, S.-T. Lee, H. Kim, Y.-T. Seo, S. Oh, J. Kim, K. Yeom, B.-G. Park, and J.-H. Lee, “On-chip training spiking neural networks using approximated backpropagation with analog synaptic devices,” Frontiers in Neuron science, vol. 423, 2020.

2019

[9] S. Lim, J.-H. Bae, J.-H. Eum, S. Lee, C.-H. Kim, D. Kwon, B.-G. Park, and J.-H. Lee, “Adaptive learning rule for hardware-based deep neural networks using electronic synapse devices,” Neural Computing and Applications, vol. 31, no. 11, 2019. 

[8] S.-T. Lee, S. Lim, N.-Y. Choi, J.-H. Bae, D. Kwon, B.-G. Park, and J.-H. Lee, “Operation scheme of multi-layer neural networks using NAND flash memory as high-density synaptic devices,” IEEE Journal of Electron Devices Society, vol. 7, 2019.

[7] J.-H. Bae, S. Lim, D. Kwon, S.-T. Lee, H. Kim, and J.-H. Lee, “Gated Schottky Diode-Type Synaptic Devices with a Field-Plate Structure to Reduce the Forward Current,” Journal of Nanoscience and Nanotechnology, vol. 19, no. 10, 2019.

[6] S. Y. Woo, K.-B. Choi, S. Lim, S.-T. Lee. C.-H. Kim, W.-M. Kang, D. Kwon, J.-H. Bae, B.-G. Park, and J.-H. Lee, “Synaptic device using a floating fin-body MOSFET with memory functionality for neural network,” Solid-State Electronics, vol. 156, 2019.

[5] D. Kwon*, S. Lim, J.-H. Eum, S.-T. Lee, J.-H. Bae, H. Kim, C.-H. Kim, B.-G. Park, and J.-H. Lee, “Highly Reliable Inference System of Neural Networks Using Gated Schottky Diodes,” IEEE Journal of the Electron Devices Society, vol. 7, 2019. (Co-First Author)

[4] J.-H. Bae, S. Lim, D. Kwon, J.-H. Eum, S.-T. Lee, H. Kim, B.-G. Park, and J.-H. Lee, “Near-linear potentiation mechanism of gated Schottky diode as a synaptic device,” IEEE Journal of the Electron Devices Society, vol. 7, 2019.

[3] J.-H. Bae, H. Kim, D. Kwon, S. Lim, S.-T. Lee, B.-G. Park, and J.-H. Lee, “Reconfigurable field-effect transistor as a synaptic device for XNOR binary neural network,” IEEE Electron Device Letters, vol. 40, no. 4, 2019.

2018

[2] D. Kwon, S. Lim, J.-H. Bae, S.-T. Lee, H. Kim, B.-G. Park, and J.-H. Lee, “Adaptive weight quantization method for nonlinear synaptic devices,” IEEE Transactions on Electron Devices, vol. 66, no. 1, 2018. 

[1] C.-H. Kim, S. Lim, S. Y. Woo, W.-M. Kang, Y.-T. Seo, S.-T. Lee, S. Lee, D. Kwon, S. Oh, Y. Noh, H. Kim, J. Kim, J.-H. Bae, and J.-H. Lee, “Emerging memory technologies for neuromorphic computing,” Nanotechnology, vol. 30, no. 3, 2018.