Publications

Thesis

B. Yuce, "Fault Attacks on Embedded Software: New Directions in Modeling, Design, and Mitigation," Ph.D. dissertation, 2017.
N.F. Ghalaty, "Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Techniques," Ph.D. dissertation, 2016.
S. Gujar, "Detecting Electromagnetic Injection Attack on FPGAs Using In Situ Timing Sensors,"M.S. thesis, 2018.
M. Ghodrati, "Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure," M.S. thesis, 2018.
C. Patrick, "Software Protection against Fault and Side Channel Attacks," M.S. thesis, 2017.
C. Deshpande, "Hardware Fault Attack Detection Methods for Secure Embedded Systems," M.S. thesis, 2017.

Journal Publications

B. Yuce, C. Deshpande, M. Ghodrati, A. Bendre, L. Nazhandali, P. Schaumont, "A Secure Exception Mode for Fault-Attack-Resistant Processing," IEEE Transactions on Secure and Dependable Computing, April 2018.
B. Yuce, P. Schaumont, M. Witteman, "Fault Attacks on Secure Embedded Software: Threats, Design and Evaluation," Springer Journal of Hardware and Systems Security, May 2018.
B. Yuce, N. F. Ghalaty, C. Deshpande, H. Santapuri, C. Patrick, L. Nazhandali, P. Schaumont "Analyzing the Fault Injection Sensitivity of Embedded Software" ACM Transactions on Embedded Computing Systems, 16(4), article 95, September 2017.
N. F. Ghalaty, B. Yuce, P. Schaumont, "Analyzing the Efficiency of Biased-Fault Based Attacks," IEEE Embedded Systems Letters, 8(2):33-36, 2016. (extended version IACR ePrint 2015/663).

Patents

B. Yuce, N.F. Ghalaty, P. Schaumont, "Microprocessor Fault Detection and Response System," U.S. Patent Application 15/596876, 11/30/2017.

Conference Publications

M. Ghodrati, S. Gujar, C. Deshpande, B. Yuce, P. Schaumont, L. Nazhandali, "Inducing Local Timing Fault through EM Injection," 2018 Design Automation Conference (DAC 2018), June 2018.
C. Deshpande, B. Yuce, P. Schaumont and L. Nazhandali, "Employing Dual-complementary Flip-Flops to Detect EMFI Attacks," 2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Beijing, CN, October 2017.
N.F. Galathy, B. Yuce, P. Schaumont. "A Systematic Approach to Fault Attack Resistant Design," in S. Bhunia, S. Ray, S. Sur-Kolay Eds., "Fundamentals of IP and SoC Security," Springer, 2017.
C. Patrick, B. Yuce, N. Farhady Ghalaty, P. Schaumont, "Lightweight Fault Attack Resistance in Software Using Intra-Instruction Redundancy," Selected Areas in Cryptography (SAC 2016), St. John's, Canada, August 2016. (preprint on IACR ePrint 2016/850).
B. Yuce, N. Farhady Ghalaty, H. Santapuri, C. Deshpande, C. Patrick, P. Schaumont, "Software Fault Resistance is Futile: Effective Single-glitch Attacks," Fault Diagnosis and Tolerance in Cryptography (FDTC 2016), Santa Barbara, CA, August 2016.
C. Deshpande, B. Yuce, N. F. Ghalaty, D. Ganta, P. Schaumont, L. Nazhandali, "A Configurable and Lightweight Timing Monitor for Fault Attack Detection," IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, July 2016.
B. Yuce, N. Farhady Ghalaty, C. Deshpande, C. Patrick, L. Nazhandali, P. Schaumont, "FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response," ACM Hardware and Architectural Support for Security and Privacy (HASP) 2016, Seoul, Korea, June 2016.
B. Yuce, N. Farhady Ghalaty, P. Schaumont, "Improving Fault Attacks on Embedded Software using RISC Pipeline Characterization" Fault Diagnosis and Tolerance in Cryptography (FDTC 2015), St Malo, France, September 2015.
N. F. Ghalaty, B. Yuce, P. Schaumont, "Differential Fault Intensity Analysis on PRESENT and LED Block Ciphers," sixth International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2015), LNCS 9064, 174-188, July 2015.
B. Yuce, N. F. Ghalaty, P. Schaumont, "TVVF: Estimating the Vulnerability of Hardware Cryptosystems against Timing Violation Attacks," IEEE International Symposium on Hardware Oriented Security and Trust (HOST-2015), 72-77, May 2015
N. F. Ghalaty, B. Yuce, M. Taha, P. Schaumont, "Differential Fault Intensity Analysis,", 11th Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2014), Busan, Korea, September 2014.