FAME v1

FAME v1

The Fault-Attack Aware Microprocessor Extensions (FAME) chip is a processor with built-in fault-sensing capability. The chip has the ability to react to a fault injection through a software trap. FAME v1 includes an in-order RISC processor with secure fault-attack resistant extensions. The processor implements the SPARC-V8 instruction set (LEON-3). The processor is manufactured in 180 nm TSMC process on a 5x5 sqmm. packaged die. The processor core is based on the open-source, synthesizable 32-bit LEON3-design.

Fault-Attack Resistant Core

• LEON-3 32-bit RISC core with FAME extensions and on-chip memory. The core contains 64KB of main memory, 2KB of data cache and 1KB of instruction cache. The genuine LEON-3 core was modified with FAME extensions as described below.
• The low-level hardware redundancy in the core is provided through Fault Recover Registers (FRR), which cover the exception and writeback stages of the pipeline including the Program Counter, Status Flags, Register File Destination Address, Register Window Pointer, and Result Value.
• The timing fault-sensor is constructed from a canary flip-flop tuned to the slowest critical path of the design. The sensor is configurable to accommodate for process variations.
• The core is capable of issuing secure trap upon detection of a timing fault from the fault sensor. The secure trap will freeze the redundant storage in the pipeline and transfer control to the secure trap. During the secure trap, the FRR remain frozen. When the timing fault sensor detects a new fault injection during the handling of the trap, the trap handler will be restarted. This ensures completion of the fault handler, even under repeated fault injection.

Fault-attack Analysis Features

The fault-attack analysis features of the chip allow an in-depth analysis of the effects of fault injection.

• A dual Debug Support Interface connects the microprocesssor to a computer for real-time, in-system programming and debugging through Universal Asychronous Receiver/Transmitter (UART). The debugging controller connects to a host computer, which runs a debug monitor used to debug LEON3 based SOC designs. The debug software along with the debug interface is used to load the compiled-C code and program data into the program memory.
• The Fault-attack Debug Environment allows post-fault injection analysis of all major registers in the processor, including those that are not visible through traditional debug infrastructure. Through a scan interface, a snapshot of the pipeline can be taken after fault injection, such that the detailed impact of a fault injection can be analyzed.
• The Fault-attack Debug Environment also offers improved fault controllability helping us to precisely inject faults and to calibrate the fault sensor. The processor generates external trigger signals, which are configured by the LEON3 program counter reaching specific values. These trigger signals are then used to drive external fault injection equipment.