This project focused on the presents the super sample rate (SSR) design for digital up converter (DUC) and digital down converter (DDC) for single carrier communication. The design aimed at the development of 5G New Radio (NR) physical layer with Zynq UltraScale+ RFSoC device which have multiple RF DACs and ADCs for direct digital synthesis. The DUC is digital front end (DFE) element that up samples the signal from communication system’s symbol rate to RF DAC conversion rate at the transmitter side. The DDC decreases the sampling rate of signal from RF ADC conversion rate to appropriate baseband signal output data rate. Both DFE elements are designed in System Generator 2019.1 and detailed resources utilization summaries are developed through Vivado implementation for ZYNQ-7 ZC702 Evaluation board. The testing and validation of the design is carried out through Additive Wide Gaussian Noise (AWGN) channel with noise power set to 30dB below the signal level and error vector magnitude (EVM) is reported to be less than 12.5% under QAM-16.
This implementation is considering single carrier/channel implementation for SSR based DSP mixing and filtering. The initial design is restricted to QAM-16. The symbol rate of communication system is taken to be 25Msymbol/s which is equivalent to 100Mbits/s data rate. The input quantization bits are limited to 5.
The sampling rate of DAC and ADC is 2GHz so that SSR value can be restricted below 10 for simpler design. The selection of high sampling rate can have repercussions later. The carrier frequency is 500MHz.
System clock is selected to be around 400MHz to take advantage the high design frequency through FIR compiler 7.2. The FIR compiler 7.2 can withstand clock frequency more than 400MHz easily. Furthermore, DDS compiler maximum design frequency is also considerably high. This choice will let us have 𝑆𝑆𝑅=2/0.4=5 which is neither too large nor too small.
Digital Up Converter (DUC) in System Generator using super sample rate filters
Digital Down Converter (DDC) in System Generator using super sample rate filter
Constellation Diagram for QAM-16 received signal at the receiver through AWGN channel where noise power was set 25dB below the desired signal
A multiplexer based area efficient and fast circular rotation mode based coordinate digital rotation computer (CORDIC) design is proposed. The direction of rotation is predicted from initial angle’s binary representation for parallel computation. The proposed design solves the issue of high number of micro rotations with help of multiplexers for high-bit width. Analysis shows significant reduction in critical path delay and resources in term of look up table (LUTs), considering FPGA as an implementation platform, in comparison to previous parallel CORDIC implementations. Comparison with conventional CORDIC, the proposed structure is more than 40% area efficient.
The idea is validated by implementing 3 sample designs in Vivado 2018.2 for Zynq- xc7z010-1clg400 board.
This project investigates the implementation of infinite impulse response (IIR) filter for audio filtration for OMAP-L138 DSP kit. Circular buffer is used to store 4 second audio which is then filtered in real time through combination of low pass, high pass and band pass filters in parallel. Memory and execution speed profiling for program is carried out through memory allocation and DSP/BIOS clock for both C and Linear Assembly (LA) code. To reduce the cycle counts, greater memory bandwidth, parallelism through division in to equivalent pair of function units and multiple Periodic function manager (PRD) objects is utilized. Compiler automatic optimization options are not used. The simulations is carried out in Code Composer Studio 6 and result is shown in time and frequency domain.