Publication

International Journal

1.  A.F. Tasch, H. Shin, C. Park, J. Alvis, S. Novak, and J. Pfiester, "Accurate Profile Simulation Parameters for BF Implants in Pre-Amorphized Silicon", IEEE Trans. on Electron Devices, ED-36, No. 1, pp. 149-152, 1989.

2. A.F. Tasch, H. Shin, C. Park, J. Alvis, and S. Novak, " An Improved Approach to Accurately Model Shallow B and BF2 Implants in Silicon", J. Electrochemical Soc., Vol. 136, No. 3, pp. 810-814, 1989.

3. H. Shin, A.F. Tasch, C.M. Maziar, and S.K. Banerjee, " A New Approach to Verify and Derive a Transverse-Field-Dependent Mobility Model for Electrons in MOS Inversion Layers", IEEE Trans. on Electron Devices, ED-36, No. 6, pp. 1117-1124, 1989.

4. A.F. Tasch, H, Shin, C.M. Maziar, "New Submicron MOSFET Structural Concept for Suppression of Hot Carrier", IEE Electronics Letters, Vol. 26, No. 1, pp. 39-41, 1990.

5. A.F. Tasch, H. Shin, T.J. Bordelon, and C.M. Maziar, "Limitations of LDD Types of Structures in Deep Submicron MOS Technology", IEEE Electron Device Letters, EDL-11. No. 11, pp. 517-519, 1990.

6. H. Shin, G.M. Yeric, A.F. Tasch, and C.M. Maziar, "Physically-based Models for Effective Mobility and Local-Field Mobility of Electrons in MOS Inversion Layers", Solid-State Electronics, Vol. 34, No. 6, pp. 545-552, 1991.

7. V.M. Agostinelli, Jr., H. Shin, and A.F. Tasch, "A Comprehensive Model of Inversion Layer Hole Mobility for Simulation of Submicron MOSFETs", IEEE Trans. on Electron Devices, ED-38, No. 1, pp. 151-159, 1991.

8. H. Shin, A.F. Tasch, T.J. Bordelon, and C.M. Maziar, "MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions: A New Structural Approach", IEEE Trans. on Electron Devices,, ED-39, No. 8, pp. 1922-1927, 1992.

9. H. Hwang, H. Shin, D.G. Kang, and D.H. Ju, "Current-Crowding Effect in Diagonal MOSFET's", IEEE Electron Device Letters, EDL-14, No. 6, pp. 289-291, 1993.

10. J.S. Goo, H. Shin, H. Hwang, D.G. Kang, and D.H. Ju, "Physical Analysis for Saturation Behavior of Hot-Carrier Degradation in Lightly Doped Drain N-Channel Metal-Oxide-Semiconductor Field Effect Transistor", Jpn. J. Applied Physics, Vol. 33, No. 1B, pp. 606-611, 1994.

11. H. Hwang, J.S. Goo, H.Y. Kwon, and H. Shin, "Anomalous Hot Carrier Degradation of nMOSFET's at Elevated Temperature Due to The Length of Velocity Saturation Region", IEEE Electron Device Letters, EDL-16, No. 4, pp. 148-150, 1995.

12. 12. J.S. Goo, Y.G. Kim, H. I'Yee, H.Y. Kwon, and H. Shin, "An Analytical Model for Hot-Carrier-Induced Degradation of Deep-Submicron n-Channel LDD MOSFETs", Solid-State Electronics, Vol. 38, No. 6, pp. 1191-1196, 1995.

13. H. Shin, "Model for Roll-off Behaviour of Electron Effective Mobility from Universal Curve", IEE Electronics Letters, Vol. 31, No. 20, pp. 1789-1791, 1995.

14. H. Shin, "Unified Model for Junction Size, Substrate Doping, and Energy Dependence of α-particle-induced Charge Collection", IEE Electronics Letters, Vol. 32, No. 20, pp. 1880-1882, 1996.

15. H. Shin, C. Lee, S.W. Hwang, B.G. Park, Y.J. Park, and H.S. Min, "Channel Length Independent Subthreshold Characteristics in Submicron MOSFET's", IEEE Electron Device Letters, EDL-19, No. 4, pp. 137-139, 1998.

16. H. Shin and S.J. Lee, "An 0.1-mm Asymmetric Halo by Large-Angle-Tilt Implant (AHLATI) MOSFET for High Performance and Reliability", IEEE Trans. on Electron Devices, ED-46, No. 4, pp. 820-822, 1999.

17. H. Shin and N.M. Kim, "Aomalous Effect of Trench-Oxide Depth on Alpha-Particle-Induced Charge Collection",IEEE Electron Device Letters, EDL-20, No. 6, pp. 280-282, 1999.

18. H. Shin, "Modeling of Alpha-Particle-Induced Soft Error Rate in DRAM", IEEE Trans. on Electron Devices, ED-46, No. 9, pp. 1850-1857, 1999.

19. W. Sun, J. Park, and H. Shin, "Influence of Trench-Oxide Depth on Junction-Size Dependence of α-Particle-Induced Charge Collection", IEE Electronics Letters, Vol. 36, No. 13, pp. 1152-1153, 2000.

20. C. Lee, J.S. Kim, H. Shin, Y.J. Park, and H.S. Min, "A New Hole Mobility Model for Hydrodynamic Simulation", Microelectronics Reliability, Vol. 40, No. 12, pp. 2019-2022, 2000.

21. C. Ryou, S.W. Hwang, H. Shin, C. Lee, Y.J. Park, and H.S. Min, "Three-dimensional Simulation of Discrete Oxide Charge Effects in 0.1um MOSFETs", Solid-State Electronics, Vol. 45, No. 7, pp. 1165-1172, 2001.

22. 22. H. Lee, J.H. Lee, H. Shin, Y.J. Park, and H.S. Min, "Low-frequency noise degradation caused by STI interface effects in SOI-MOSFETs", IEEE Electron Device Letters, EDL-22, No. 9, pp. 449-451, 2001.

23. S.J. Hong, H. Nah, Y.J. Park, H.S. Min, C. Lee, and H. Shin, "Analysis of the Accuracy of the Local Temperature Noise Sources for the Impedance Field Method Using the Monte Carlo Method", J. of the Korean Physical Society, Vol. 40, No. 1, pp. 77-81, 2002.

24. H. Lee, J.H. Lee, H. Shin, Y.J. Park, and H.S. Min, "An Anomalous Device Degradation of SOI Narrow Width Devices Caused by STI Edge Influence", IEEE Trans. on Electron Devices, ED-49, No. 4, pp. 605-612, 2002.

25. W. Sun and H. Shin, "New Method to Extract the Lateral Profile of Hot-Carrier-Induced Nits by Using the Charge Pumping Method", J. of the Korean Physical Society, Vol. 40, No. 4, pp. 636-641, 2002.

26. H. Lee, Y.J. Park, H.S. Min, H. Shin and D.G. Kang, "Reduction of Reverse Short-Channel Effect in High-Energy Implanted Retrograde Well", J. of the Korean Physical Society, Vol. 40, No. 4, pp. 649-652, 2002.

27. H. Lee, Y.J. Park, H.S. Min, J.H. Lee, H. Shin, W. Sun and D.G. Kang, "Effects of Shallow Trench Isolation on Silicon-on-Insulator Devices for Mixed Signal Processing", J. of the Korean Physical Society, Vol. 40, No. 4, pp. 653-657, 2002.

28. J. Park S. Lee, H. Shin and R.W. Dutton, "Analytical analysis of short-channel effects in MOSFETs for sub-100 nm technology", IEE Electronics Letters, Vol. 38, No. 20, pp. 1222-1223, 2002.

29. H. Nah, Y. Park, H. Min, C. Lee, and H. Shin, "Investigation of Noise Characteristics of pn Diodes by Using a Device Simulator", J. of the Korean Physical Society, Vol. 41, No. 6, pp. 888-891, 2002.

30. J. Kim, J. Lee, S. Lee, and H. Shin, "Macro Model and Sense Amplifier for a MRAM", J. of the Korean Physical Society, Vol. 41, No. 6, pp. 896-901, 2002.

31. K. Lee, J. Park, and H. Shin, "Quantum Effects in CMOS Devices", J. of the Korean Physical Society, Vol. 41, No. 6, pp. 902-907, 2002.

32. D.J. Kim, J.H. Ko, C.H. Cho, Y.I. Park, D.W. Kang, K.S. Min, D.M. Kim, S.J. Lee and H.S. Shin, "High Cell-Efficiency Synchronous MRAM Adopting Unified Bit-Line Cache ", IEE Electronics Letters, Vol. 39, No. 16, pp. 1166-1167, 2003.  

33. E.J. Jang, S.Y. Lee, H.J. Kim, H. Shin, S.J. Lee, and D.J. Kim, "A Sensing Circuit for MRAM based on 2MTJ-2T Structure", Current Applied Physics, Vol. 4, No. 1, pp. 19-24, 2004.

34. H. Lee and H. Shin, "Analysis of the TSi-Dependent Subthreshold Characteristics in Lightly-Doped Asymmetric Double-Gate MOSFETs", J. of the Korean Physical Society, Vol. 44, No. 1, pp. 56-59, 2004. 

35. J. Lee and H. Shin, "Evanescent-Mode Analysis of Short-Channel Effects in MOSFETs", J. of the Korean Physical Society, Vol. 44, No. 1, pp. 50-55, 2004.

36. K. Lee, Y.J. Park, H.S. Min, C. Lee, H. Shin,  "An Efficient Method Including the Non-Quasistatic Effect for Frequency-Domain Simulation of Short Channel MOSFETs", J. of the Korean Physical Society, Vol. 44, No. 1, pp. 73-78, 2004.

37. J. Park, H. Shin, D. Connelly, D. Yergeau, Z. Yu, and R. Dutton,  "Analysis of 2-D Quantum Effects in the Poly-Gate and their Impact on the Short-Channel Effects in Double-Gate MOSFETs via the Density-Gradient Method", Solid-State Electronics, Vol. 48, No. 7, pp. 1163-1168, 2004.

38. H. Kim, S. Lee, S. Lee, H. Shin, and D. Kim, "A Novel Sensing Circuit for High Speed Synchronous Magneto-Resistive RAM", Jpn. J. of Applied Physics, Vol. 43, No. 4B, pp. 2226-2229, 2004.

39. S. Lee, H. Kim, S. Lee, and H. Shin, "A New Reference Cell for 1T-1MTJ MRAM”, Journal of Semiconductor Technology and Science, Vol. 4, No. 2, pp. 110-116, 2004.

40. J. Kim, H. Shin, C. Lee, Y. Park, and H. Min, "A New Weight Redistribution Technique for Electron-Electron Scattering in the MC Simulation", IEEE Trans. on Electron Devices, ED-51, No. 9, pp. 1448-1454, 2004.

41. J. Park, J. Lee, S. Lee, H. Shin, S. Jin, Y. Park, and H. Min, "A Unified Mobility Model for Quantum Mechanical Simulation of MOSFETs", J. of the Korean Physical Society, Vol. 45, No. 5, pp. 1332-1337, 2004.

42. S. Lee, S. Lee, H. Shin, and D. Kim, "Advanced HSPICE Macromodel for Magnetic Tunnel Junction", Jpn. J. of Applied Physics, Vol. 44, No. 4B, pp. 2696-2700, 2005.

43. K. Lee, C. Lee, H. Shin, Y. Park, and H. Min, "Efficient Frequency-Domain Simulation Technique for Short-Channel MOSFET", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 862-868, 2005.

44. J. Park, S. Lee, Y. Jhee, and H. Shin, "Charge-Based Analytical Current Model for Asymmetric Double-Gate MOSFETs",  J. of the Korean Physical Society,  Vol. 47, No. 3, pp. S392-S396, 2005.

45. S. Lee, N. Kim, H. Yang, G. Lee, S. Lee, and H. Shin, "The 3-bit Gray Counter based on Magnetic-Tunnel-Junction Elements", IEEE Trans. on Magnetics, Vol. 43, No. 6, pp. 2677-2679, 2007.

46. S. Lee, S. Choa, S. Lee, and H. Shin, “Magneto-Logic Device Based on a Single-Layer Magnetic-Tunnel Junction", IEEE Trans. on  Electron Devices, vol. 54, no. 8, pp. 2040-2044, 2007.

47. S. Lee, S. Seo, S. Lee, and H. Shin, "A Full Adder Design Using Serially Connected Single-Layer Magnetic Tunnel Junction Elements", IEEE Trans. on  Electron Devices, vol. 55, no. 3, pp. 890-895, 2008.

48. S. Lee, G. Lee, H. Lee, S. Lee, and H. Shin, "Design of Reconfigurable Logic Circuits based on Single-Layer Magnetic-Tunnel-Junction Elements", Jpn. J. of Applied Physics, vol. 47, no. 4, pp. 3264-3268, 2008.

49. A. Son, J. Kim, N. Jeong, J. Choi, and H. Shin, "Improved Explicit Current-Voltage Model for Long-Channel Undoped Surrounding-Gate Metal Oxide Semiconductor Field Effect Transistor", Jpn. J. of Applied Physics, vol. 48, no. 4, pp. 04C035-1 ~ 04C035-4, 2009.

50. H. Lee, S. Kim, S. Lee, S. Lee, and H. Shin, "Design of Logic Module based on Magnetic-Tunnel-Junction Elements for Nonvolatile Field-Programmable Gate Array", Jpn. J. of Applied Physics, vol. 48, no. 4, pp. 04C197-1 ~ 04C197-4, 2009.

51. S. Lee, H. Lee, S. Kim, S. Lee, and H. Shin, "A Novel Macro-Model for Spin-Transfer-Torque based Magnetic-Tunnel-Junction Elements", Solid-State Electronics, vol. 54, no. 4, pp. 497-503, 2010.

52. S. Kim, S. Lee, and H. Shin, “Advanced Macro-Model with Pulse-Width Dependent Switching Characteristic for Spin-Transfer-Torque based Magnetic-Tunnel-Junction Elements”, Jpn. J. of Applied Physics, vol. 49, no. 4, pp. 04DM07-1~04DM07-6, 2010.

53. J. Kim, W. Sun, S. Park, H. Lim and H. Shin, “A Compact Model of Gate-Voltage-Dependent Quantum Effects in Short-Channel Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors,” Journal of Semiconductor Technology and Science, vol. 11, no. 4, pp. 278-286, 2011.

54. H. Lim, S. Ahn, S. Lee, and H. Shin, “Physics-Based SPICE Model of Spin-Torque Oscillators”, Jpn. J. of Applied Physics, vol. 51, no. 4, pp. 04DM03-1~04DM03-5, 2012.

55. S. Ahn, H. Lim, H. Shin, and S. Lee, “Analytic Model of Spin-Torque Oscillators (STO) for Circuit-Level Simulation“, Journal of Semiconductor Technology and Science, vol. 13, no. 1, pp. 28-33, 2013.

56. S. Ahn, H. Lim, M. Kim, H. Shin, and S. Lee, “Circuit-Level Model of Phase-Locked Spin-Torque Oscillators”, Jpn. J. of Applied Physics, vol. 52, no. 4, pp. 04CM08-1~04CM08-4, 2013.

57. H. Lim, S. Ahn, M. Kim, S. Lee, and H. Shin, “A New Circuit Model for Spin-Torque Oscillator Including Perpendicular Torque of Magnetic Tunnel Junction”, Advances in Condensed Matter Physics, vol. 2013, pp. 169312-1~169312-6, 2013.

58. 58. J. Kim, W. Sun, and H. Shin, “A new I-V model for surrounding-gate MOSFET considering gate-voltage-dependent quantum effect”, International Journal of Electronics, vol. 100, no. 8, pp. 1072-1079, 2013.

59. M. Kim, H. Lim, S. Ahn, S. Lee, and H. Shin, “Advanced Circuit-Level Model of Magnetic Tunnel Junction-based Spin-Torque Oscillator with Perpendicular Anisotropy Field", Journal of Semiconductor Technology and Science, vol. 13, no. 6, pp. 556-561, 2013.

60. H. Lim, S. Lee, and H. Shin, “Unified Analytical Model for Switching Behavior of Magnetic Tunnel Junction“, IEEE Electron Device Letters, vol. 35, no. 2, pp. 193-195, 2014.

61. W. Sun and H. Shin, “Optimization of uniaxial stress for high electron mobility on biaxially-strained n-MOSFETs”, Solid-State Electronics, vol. 94, pp. 23-27, 2014.

62. W. Sun and H. Shin, “Temperature Dependence of Electron Mobility in Uniaxial Strained nMOSFETs”, Journal of Semiconductor Technology and Science, vol. 14, no. 2, pp. 146-152, 2014.

63. M. Kim and H. Shin, “Anomalous drain-induced barrier lowering effect of thin-film transistors due to capacitive coupling voltage of light-shield metal”, Electronics Letters, vol. 50, no. 15, pp. 1093-1095, 2014.

64. W. Sun, S. Choi, and H. Shin, “Substrate Doping Concentration Dependence of Electron Mobility Enhancement in Uniaxial Strained (110)/<110> nMOSFETs”, Journal of Semiconductor Technology and Science, vol. 14, no. 10, pp. 518-524, 2014.

65. H. Lim, S. Lee, and H. Shin, “Advanced Circuit-Level Model for Temperature-Sensitive Read/Write Operation of a Magnetic Tunnel Junction”, IEEE Transactions on Electron Devices, vol. 62. No. 2, pp. 666-672, 2015.

66. S. Choi, W. Sun, and H. Shin, “Analysis of stress-induced mobility enhancement on (100)-oriented single- and double-gate n-MOSFETs using silicon-thickness-dependent deformation potential”, Semiconductor Science and Technology, vol. 30, no. 4, p. 045009, 2015.

67. S. Choi, W. Sun, and H. Shin, “Analysis of the Substantial Reduction of Strain-induced Mobility Enhancement in (110)-oriented Ultrathin Double-Gate MOSFETs”, Applied Physics Express, vol. 9, no. 1, p. 014201, 2016.

68. H. Lim, W. Sun, and H. Shin, “ReRAM Crossbar Array: Reduction of Access Time by Reducing the Parasitic Capacitance of the Selector Device”, IEEE Transactions on Electron Devices, vol. 63. no. 2, pp. 873-876, 2016.

69. W. Sun, S. Choi, H. Lim, and H. Shin, “Guideline model for the bias-scheme-dependent power consumption of a resistive random access memory crossbar array , Jpn. J. of Applied Physics, vol. 55, no. 4, pp. 04EE10-1~04EE10-5, 2016.

70. M. Kim, W. Sun, M. Shin, K. Kim. J. Kang, and H. Shin, “Anomalous Capacitance Characteristics of TFTs with LDD Structures in the Saturation Region”, Semiconductor Science and Technology, vol. 31, no. 5, p. 055015, 2016.

71. S. Choi, W. Sun, I. Lee, and H. Shin, “Analysis of Stress Effect on (110)-Oriented Single-Gate SOI nMOSFETs Using a Silicon-Thickness-Dependent Deformation Potential”, Journal of Nanoscience and Nanotechnology. vol. 16, no, 5, pp. 5150-5154, 2016.

72. H. Lim, S. Lee, and H. Shin, “A Survey on the Modeling of Magnetic Tunnel Junctions for Circuit Simulation“, Active and Passive Electronic Components, vol. 2016, pp. 3858621-1~3858621-12, 2016.

73. W. Sun, S. Choi, and H. Shin, “A new bias scheme for a low power consumption ReRAM crossbar array”, Semiconductor Science and Technology, vol. 31, no. 8, p. 085009, 2016.

74. H. Lim, S. Lee, and H. Shin, “Switching Time and Stability Evaluation for Writing Operation of STT-MRAM Crossbar Array”, IEEE Transactions on Electron Devices, vol. 63. no. 10, pp. 3914-3921, 2016.

75. I. Lee, M. Kim, M. Shin, and H. Shin, “A new method for determining the subgap density of states in n-/p-type Low-Temperature Polycrystalline-Silicon Thin-Film Transistors“, Journal of Nanoscience and Nanotechnology. vol. 17, no, 5, pp. 2951-2958, 2017.

76. S. Choi, W. Sun, and H. Shin, “A guideline for electron mobility enhancement in uniaxially-strained (100)/<100> and (110)/<110> FinFETs,” Journal of Nanoscience and Nanotechnology. vol. 17, no, 5, pp. 2999-3004, 2017.

77. M. Kim, W. Sun, J. Kang, and H. Shin, “The effect of a source-contacted light shield on the electrical characteristics of an LTPS TFT“, Semiconductor Science and Technology, vol. 32, no. 8, p. 085001, 2017.

78. S. Choi, W. Sun, and H. Shin, “New modeling method for the dielectric relaxation of a DRAM cell capacitor”, Solid State Electronics, Vol. 140, pp. 29-33, 2018.

79. W. Sun, S. Choi, and H. Shin, “Read margin analysis of crossbar arrays using the cell-variability-aware simulation method”, Solid State Electronics, Vol. 140, pp. 55-58, 2018.

80. S. Choi. W. Sun, and H. Shin, “Analysis of Read Margin and Write Power Consumption of a 3-D Vertical RRAM (VRRAM) Crossbar Array”, IEEE J. of the Electron Devices Society, Vol. 6, no, 1, pp. 1192-1196, 2018.

81. S. Choi. W. Sun, and H. Shin, “Analysis of Cell Variability Impact on a 3-D Vertical RRAM (VRRAM) Crossbar Array Using a Modified Lumping Method”, IEEE Transactions on Electron Devices, vol. 66. no. 1, pp. 759-765, 2019.

82. E. Yu, S. Cho, H. Shin, and B. Park, “A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency”, IEEE Electron Device Letters, vol. 40, no. 4, pp. 562-565, 2019.

83. J. Seo, Y. Yoon, E. Yu, W. Sun, H. Shin, I. Kang, J. Lee, and S. Cho, “Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect”, IEEE Electron Device Letters, vol. 40, no. 4, pp. 566-569, 2019.

84. B. Kim, S. Jo, W. Sun, and H. Shin, “Analysis of the Memristor-Based Crossbar Synapse for Neuromorphic Systems”, Journal of Nanoscience and Nanotechnology. vol. 19, no. 10, pp. 6703-6709, 2019.

85. S. Jo, W. Sun, B. Kim, S. Kim, J. Park, and H. Shin, “Memristor Neural Network Training with Clock Synchronous Neuromorphic System”, Micromachines, vol. 10, no. 6, p. 384, 2019.

86. H. Kim, I. Kang, S. Cho, W. Sun, and H. Shin, “Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode”, Semiconductor Science and Technology, vol. 34, no. 10, p. 105007, 2019.

87. H. Kim, S. Yoo, I, Kang, S. Cho, W. Sun, and H. Shin, “Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM”, Micromachines, vol, 11, no. 2, p. 228, 2020.

88. W. Sun, S. Choi, B. Kim, and H. Shin, “Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses”, Journal of Nanoscience and Nanotechnology. vol. 20, no. 8, pp. 4730~4734, 2020.

89. Y. Choi, M. Kim, J. Park, and H. Shin, “Analysis of Organic Light-Emitting Diode SPICE Models with Constant or Voltage-Dependent Components”, Journal of Nanoscience and Nanotechnology. vol. 20, no. 8, pp. 4773~4777, 2020.

90. Y. Jeong, I. Kang, S. Cho, J. Park, and H. Shin, “Charge Based Current–Voltage Model for the Silicon on Insulator Junctionless Field-Effect Transistor”, Journal of Nanoscience and Nanotechnology. vol. 20, no. 8, pp. 4920~4925, 2020.

91. S. Yoo, W. Sun, and H. Shin, “Optimization Considerations for Short Channel Poly-Si 1T-DRAM”, Electronics, vol. 9, no. 6, p. 1051, 2020.

92. S. Choi, D. Kim, Y. Choi, W. Sun, and H. Shin, “Multibit-Generating Pulsewidth-Based Memristive-PUF Structure and Circuit Implementation”, Electronics, vol. 9, no. 9, p. 1446, 2020.

93. S. Yoo, W. Sun, and H. Shin, “Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM”, Micromachines, vol. 11, no. 11, p. 952, 2020.

94. Y. Choi, T. Lee, J. Park, and H. Shin, “Analysis of the transient body effect model for an LTPS TFT on a plastic substrate”, Solid State Electronics, vol. 175, no. 1, p. 107948, 2021.

95. S. Yoo, I. Kang, S. Cho, W. Sun, and H. Shin, “Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory”, Journal of Nanoscience and Nanotechnology. vol. 21, no. 8, pp. 4216~4222, 2021.

96. D. Kim. T. Kim, Y. Choi, G. Lee, J. Lee, W. Sun, B. Park, H. Kim, and H. Shin, “Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array ”, IEEE ACCESS, vol. 9, pp. 120901~120910, 2021.

97. Y. Ha, H. Shin, W. Sun, and J. Park, “Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM”, Micromachines, vol. 12, no. 10, p. 1209, 2021.

98. Y. Choi, J. Park, and H. Shin, “New Simulation Method for Dependency of Device Degradation on Bending Direction and Channel Length”, Materials, vol. 14, no. 10, p. 6167, 2021.

99. H. Chung, H. Shin, J. Park, and W. Sun, “A Unified Current-Voltage Model for Metal Oxide-Based Resistive Random-Access Memory”, Materials, vol. 16, p. 182, 2022.

100. Y. Choi, W. Sun , J. Park, and H. Shin, “Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors“, IEEE ACCESS, vol. 11. pp. 15909~15920, 2023.

101. A. Shah, E. Cho, J. Park, H. Shin, and S. Cho, “A Compact Integrate-and-Fire Neuron Circuit Embedding Operational Transconductance Amplifier for Fidelity Enhancement“, IEEE ACCESS, vol. 11. pp. 53932~53938, 2023.

Korean Journal

1. 신형순, "MOS 소자 반전층의 전자 이동도에 대한 해석적 모델", 전기전자재료학회 논문지, Vol. 9, No. 2, pp. 174-179, 1996.

2. 신형순, "LDD N-MOSFET에서 핫-캐리어 열화의 만능곡선에 관한 연구", 전기학회논문지, Vol. 45, No. 8, pp. 1234-1237, 1996.

3. 김중식, 김진양, 이찬호, 신형순, 박영준, 민홍식, "정공과 격자의 온도를 고려한 새로운 정공 이동도 모델", 전자공학회 논문지, Vol. 35, No. 8, pp. 31-37, 1998.

4. 신형순, "알파 입자에 의한 전하 수집량에 대한 통합 모델", 전자공학회 논문지, Vol. 36, No. 1, pp. 83-89, 1999.

5. 신형순, "DRAM 소프트 에러율 시뮬레이터", 전자공학회 논문지, Vol. 36, No. 2, pp. 161-167, 1999.

6. 이경호, 신형순, "고집적 DRAM에 대한 소프트 에러율", 전자공학회 논문지, Vol. 38, No. 2, pp. 87-94, 2001.

7. 박지선, 신형순, “NMOSFET의 반전층 양자 효과에 관한 연구”, 전기학회 논문지, Vol. 51C, No. 9, pp. 397-407, 2002.

8. 이성원, 이승준, 신형순, “MOSFET의 Effective Channel Length를 추출하기 위한 C-V방법의 타당성 연구”, 전자공학회 논문지, Vol. 39, No. 10, pp. 855-862, 2002.

9. 이혜림, 신형순, “Asymmetric Double-Gate MOSFET의 Subthreshold 특성 분석”, 전자공학회 논문지, Vol. 40, No. 6, pp. 379-383, 2003.

10. 이성원, 신형순, “STI구조를 갖는 nMOSFET의 채널 너비에 따른 Hot-Carrier열화 현상에 관한 연구”, 전자공학회 논문지, Vol. 40, No. 9, pp. 638-643, 2003.

11. 이지영, 신형순, “Evanescent-Mode를 이용한 MOSFET의 단채널 효과 분석”, 전자공학회 논문지, Vol. 40, No. 10, pp. 758-765, 2003.

12. 박지선, 이승준, 신형순, “폴리 게이트의 양자효과에 의한 Double-Gate MOSFET의 특성 변화 연구”, 전자공학회 논문지, Vol. 41, No. 8, pp. 629-636, 2004.

13. 이승연, 이승준, 신형순, “MRAM용 HSPICE 마크로 모델과 Midpoint Reference 발생회로에 관한 연구”, 전자공학회 논문지, Vol. 41, No. 8, pp. 717-725, 2004.

14. 이승연, 김지현, 이감영, 양희정, 이승준, 신형순, “Magnetic-Tunnel-Junction 소자를 이용한 3진 업/다운 카운터”, 전자공학회 논문지 SD편, vol. 44, no. 1, pp. 1-7, 2007.

15. 이승연, 이감영, 이현주, 이승준, 신형순, “단층 입력 구조의 Magnetic- Tunnel-Junction 소자를 이용한 4비트 그레이 카운터 ”, 전자공학회 논문지 SD편, vol. 44, no. 9, pp. 760-767, 2007.

16. 양희정, 김지현, 손애리, 강대관, 신형순, "전압분포의 선형특성을 이용한 Long-Channel Asymmetric Double-Gate MOSFET의 문턱전압 모델", 전자공학회 논문지, vol. 45, no. 2, pp. 71-76, 2008.

17. 이감영, 이승연, 이현주, 이승준, 신형순, "Local Field Switching 방식의 MRAM 설계", 전자공학회 논문지, vol. 45, no. 8, pp. 767-776, 2008.

18. 김지현, 손애리, 정나래, 신형순, “이차원 양자효과를 고려한 극미세 Double-Gate MOSFET특성분석”, 전자공학회 논문지, vol. 45, no. 10, pp. 964-971, 2008.

19. 이현주, 김소정, 이승연, 이승준, 신형순, “단층 입력 구조의 Magnetic-Tunnel-Junction 소자를 이용한 임의의 3비트 논리회로 구현을 위한 자기논리 회로 설계”, 전자공학회 논문지, vol. 45, no. 12, pp. 1133-1139, 2008.

20. 정나래, 김유진, 윤지숙, 박성민, 신형순, “Independent-Gate-Mode Double-Gate MOSFET를 이용한 RF Receiver 설계” 전자공학회 논문지, vol. 46, no. 10, pp. 819-826, 2009.

21. 김지현, 정나래, 김유진, 신형순 “Double-Gate MOSFET을 이용한 공핍형 NEMFET의 특성분석 및 최적화”, 전자공학회 논문지, vol. 46, no. 12, pp.1007-1014, 2009.

22. 김유진, 정나래, 박성민, 신형순, “Independent-Gate-Mode Double-Gate를 이용한 Optical Receiver 설계”, 전자공학회 논문지, vol. 47, no. 8, pp. 619-628, 2010.

International Conference

1. H. Shin, C.M. Maziar, S.K. Banerjee, and A.F. Tasch, "A New Modeling Approach for the Transverse-Field-Dependent Mobility of Electrons in MOS Inversion Layers", presented at TECHCON'88 Semiconductor Research Corporation, Dallas TX, October 1988.

2. T.J. Bordelon, H. Shin, A.F. Tasch, and C.M. Maziar, "A Computationally Efficient Method for Estimating Non-Local Field Impact Ionization in Submicron Si Structure", presented at Texas Research Seminars PhaseⅢ, Dallas TX, April 1989.

3. V.M. Agostinelli, Jr., H. Shin, and A.F. Tasch, "A Comprehensive Model of Inversion Layer Hole Mobility for Simulation of Submicron MOSFETs", Workshop on Numerical Modeling of Processes and Device for Integrated Circuits(NUPADⅢ), pp. 39-40, June 1990.

4. A.F. Tasch and H. Shin, "Scaling the MOS Transistor to Its Limit in ULSI", Spring Meeting of the Electrochemical Society, pp. 511-512, May 1990.

5. A.F. Tasch and H. Shin, "A New Structural Approach for Reducing Hot Carrier Generation in Deep Submicron MOSFETs", 1990 Symposium on VLSI Technology, pp. 43-44, June 1990.

6. Y.G. Kim, J.S. Goo, H. I'Yee, H. Hwang, and H. Shin, "Charge-up Induced Gate Oxide Breakdown", Digest of IEICE, pp. 67-71, June 1993.

7. J.S. Goo, H. Shin, H. Hwang, D.G. Kang, and D.H. Ju, "Universal Behavior of Hot-Carrier Degradation in LDD NMOSFET's", 1993 International Conference on Solid State Devices and Materials, pp. 35-37, August 1993.

8. H. Hwang, J.S. Goo, H. Kwon, and H. Shin, "Impact of Oxide Electric Field on Hot-Carrier Reliability Characteristics", Fall Meeting of the Electrochemical Society, October 1993.

9. H. Hwang, J.S. Goo, H.Y. Kwon, and H. Shin, "Anomalous Temperature Dependence of NMOSFET Lifetime Under Hot Electron Stress", 1994 European Solid State Device Research Conference, pp. 381-384, September 1994.

10. J.S. Goo, Y.G. Kim, H. l'Yee, H.Y. Kwon, and H. Shin, "An Analytical Hot-Carrier Degradation Model for LDD NMOSFETs", 1994 European Solid State Device Research Conference, pp. 425-428, September 1994.

11. H. Hwang, J.S. Goo, H.Y. Kwon, and H. Shin, "Enhanced Degradation of nMOSFET's under Hot Carrier Stress at Elevated Temperature Due to The Length of Velocity Saturation Region", 1994 IEEE International Integrated Reliability Workshop, pp. 138-139, October 1994.

12. H. Hwang, J.S. Goo, H.Y. Kwon, and H. Shin, "Impact of Velocity Saturation Region on nMOSFET's Hot Carrier Reliability at Elevated Temperatures", 1995 IEEE International Reliability Physics Symposium, pp. 48-50, April 1995.

13. Y. Huh, D. Yang, H. Shin, and Y. Sung, "Hot-Carrier-Induced Circuit Degradation in Actual DRAM", 1995 IEEE International Reliability Physics Symposium, pp. 72-75, April 1995.

14. H.S. Shin, C. Lee, S.W. Hwang, B.G. Park, Y.J. Park, and H.S. Min, "Anomalous Subthreshold Characteristics due to Localized Pileup of Channel Dopants in Submicron MOSFET's", International Conference on VLSI and CAD, pp. 184-186, October 1997.

15. J.S. Kim, J.Y. Kim, C. Lee, H.S. Shin, Y.J. Park, and H.S. Min, "A New Hole Mobility Model suitable for the Hydrodynamic Simulation", International Conference on VLSI and CAD, pp. 570-572, October 1997.

16. K.I. Lee, J. Kim, H.S. Shin, C. Lee, Y.J. Park, and H.S. Min, "An Efficient Frequency-Domain Analysis Technique of MOSFET Operation", International Conference on Simulation of Semiconductor Processes and Devices, pp. 186-189, September 2001.

17. H. Nah, Y.J. Park, H.S. Min, C. Lee, and H.S. Shin, "Characterization of Low-Frequency Noise of MOSFETs Using 2-D Device Simulator", International Conference on Simulation of Semiconductor Processes and Devices, pp. 400-403, September 2001.

18. H. Kim, S. Lee, S. Lee, H. Shin, and D. Kim, "A Novel Sensing Circuit for High Speed Synchronous MRAM", International Conference on Solid State Devices and Materials, pp. 652-653, September, 2003.

19. K. Lee, C. Lee, H. Shin, Y.J. Park, H.S. Min, "An Efficient Method for Frequency-Domain Simulation of Short Channel MOSFET Including the Non-Quasistatic Effect", International Conference on Simulation of Semiconductor Processes and Devices, pp. 231-234, September 2003.

20. S. Lee, S. Lee, H. Shin, and D. Kim, "An Advanced HSPICE Macro-Model for Magnetic-Tunnel-Junction", International Conference on Solid State Devices and Materials, pp. 642-643, September 2004.

21. S. Lee, J. Kim, H. Yang, G. Lee, S. Lee, and H. Shin, "3-bit Gray Counter based on a Magnetic-Tunnel-Junction Elements", 10th Joint MMM-Intermag Conference, p. 48, January 2007.

22. S. Lee, G. Lee, H. Lee, S. Lee, and H. Shin, "Design of Reconfigurable Logic Circuits based on Single-Layer Magnetic-Tunnel-Junction Elements", International Conference on Solid State Devices and Materials, pp. 684-685, September 2007.

23. S. Lee, G. Lee, S. Lee, and H. Shin, "128bit MRAM using CMOS Emulation Cell for MTJ", 2007 International SoC Design Conference, pp. 618-619, October 2007.

24. S. Lee, H. Lee, S. Lee, and H. Shin, "A Novel Macro-Model for Spin-Transfer-Torque based Magnetic-Tunnel-Junction Elements", IEEE International Magnetics Conference, p. 1112 , May 2008.

25. Y. Park, S. Lee, H. Shin, and S. Lee, "Feasibility Study on Spin-Transfer-Torque based Magnetic-Tunnel-Junction Element as a Memory Cell", International Conference on Electronics, Information, and Communication , pp. 981-984, June 2008.

26. A. Son, J. Kim, N. Jeong, J. Choi, and H. Shin, "Improved Analytic I-V Model of the Long-Channel Undoped Surrounding-Gate MOSFET", International Conference on Solid State Devices and Materials, pp. 412-413, September 2008.

27. S. Lee, H. Lee, S. Kim, S. Lee, and H. Shin, "Design of Logic Module based on Magnetic-Tunnel-Junction Elements for Nonvolatile FPGA", International Conference on Solid State Devices and Materials, pp. 668-669, September 2008.

28. S. Kim, S. Lee, and H. Shin, “Advanced Macro-Model with Pulse-Width Dependent Switching Characteristic for Spin-Transfer-Torque based Magnetic-Tunnel-Junction Elements”, International Conference on Solid State Devices and Materials, pp. 703-704, October 2009.

29. H. Lim, S. Ahm, S. Lee, and H. Shin, “Physics-based SPICE Model of Spin Torque Oscillators”, International Conference on Solid State Devices and Materials, pp. 1466-1467, Sep. 2011.

30. H. Lim, S. Ahn, M. Kim, J. Shin, J. Lee, S. Lee, and H. Shin, “A New Circuit Model for Spin-Torque Oscillator including the Perpendicular Torque of Magnetic Tunneling Junction”, 19th International Conference on Magnetism, July 2012.

31. S. Ahn, H. Lim, H. Shin, and S. Lee, “Circuit Level Model of Phase-Locked Spin Torque Oscillators”, International Conference on Solid State Devices and Materials, pp. 1201-1202, September 2012.

32. W. Sun and H. Shin, “Substrate Doping Concentration Dependence of Electron Mobility using the Effective Deformation Potential in Uniaxial Strained nMOSFETs”, IEEE TENCON 2013, October 2013.

33. W. Sun, H. Lim, W. Lee, and H. Shin, “Investigation of power dissipation for ReRAM in crossbar array architecture”, 14th Non-Volatile Memory Technology Symposium, pp. 148-149, October 2014.

34. W. Sun, H. Lim, S. Choi, and H. Shin, “Guideline Model for the Bias-Scheme-Dependent Power Consumption of a ReRAM Crossbar Array“, International Conference on Solid State Devices and Materials, pp. 132-133, September 2015.

35. M. Kim, I. Lee, H. Shin, and M. Shin, “Analysis of the Effect of the Density of States on the Characteristics of Thin-Film Transistors“, IEEE TENCON 2015, November 2015.

36. S. Choi, W. Sun, H. Lim, and H. Shin, “An Analysis of the Read Margin and Power Consumption of Crossbar ReRAM Arrays”, IEEE TENCON 2015, November 2015.

37. W. Sun and H. Shin, “Analysis of read margin of crossbar array according to selector and resistor variation“, ICEIC 2018, pp. 417=419, January 2018.

38. W. Sun, J. Park, S. Jo, J. Lee, and H. Shin, “Implementation of multi-layer neural network system for neuromorphic hardware architecture“, ICEIC 2019, pp. 74-75, January 2019.

39. Y. Choi, J. Park, and H. Shin, “Analysis of hump effect in tensile-stressed a-IGZO TFT using TCAD simulation”, ICEIC 2021, pp. 74-75, January 2021.

40. D. Kim, S. Choi, Y. Choi, J. Lee, W. Sun, and H. Shin, “The implementation of robust crossbar array-based PUF against ML attack for hardware security solution", ICEIC 2021, pp. 440-443, January 2021.

41. H. Chung, H. Shin, J. Park, and W. Sun, “A New I-V model for oxide-based resistive random access memory”. ICEIC 2022, pp. 876-878, February 2022.

42. H. Lee, S. Ko, H. Suh, G. Jeong, J. Yeo, H. Park, H. Kim, J. Kim, S. Chung, Y. Kim, J. Park, and H. Shin, “Progressive Degradation Without Physical Failure During Mounting Due to Soft Overstress in Compound HBT for RF, Mobile, and Automotive Applications”, 2022 IEEE International Reliability Physics Symposium, pp. 10C.4-1~10C.4-6, March 2022.

43. Y. Choi, J. Lee, H. Shin, and W. Sun. “Mutual authentication method between PUFs”, ICECET 2022, July 2022.

44.  H. Chung, H. Shin, W. Sun, and J. Park, “An Improved I-V model for Resistive random access memory”, ICECET 2022, July 2022.

45. H. Lee, D. Kim, J. Noh, Y. Kim, J. Park, and H. Shin, “Predictable ESD Criteria with Proposed Comparison Diagram between TLP and HBM ESD for Various Device Technologies and Different Substrates”, IEEE EDTM 2023, March 2023.

46. H. Lee, J. Park, D. Bae, K. Kim, J. Noh, Y. Kim, J. Park, and H. Shin, “Different Proposed Analysis with TCAD for Catastrophic Large Area Failure due to Radiation Stress on 4H-SiC Schottky Diode”, IEEE EDTM 2023, March 2023.

47. A. Shah, Y. Lee, J. Park, H. Shin, and S. Cho, “Design and Optimization of an All-Transistor Integrate-and-Fire Neuron Circuit with Schmitt Trigger and Active Capacitors ”, ITC-CSCC 2024, July 2024.

Korean Conference

1. 신형순, "A New Structural Approach for Deep Submicron MOSFETs", 제1회 젊은 공 학도를 위한 반도체 Workshop, pp. 160-165, March 1991.

2. 황현상, 신형순, 강대관, 주동혁, "Current Crowding Effect of Diagonal MOSFETs", 제3 회 젊은 공학도를 위한 반도체 Workshop, pp. 8-9, Feb. 1993.

3. 구정석, 신형순, 황현상, 강대관, 주동혁, "LDD NMOSFET Hot-Carrier 노쇠화의 포화현 상 원인 규명", 제3회 젊은 공학도를 위한 반도체 Workshop, pp. 16-19, Feb. 1993.

4. 홍성준, 신형순, 이찬호, 박영준, 민홍식, "Effect of Temperature Gradient on Electron Mobility in Submicron Silicon Devices", 제4회 한국 반도체 학술대회, pp. 501-502, Feb. 1997.

5. Jin-Yang Kim, Chan-Ho Lee, Hyung-soon Shin, Young-June Park, and Hong-Shick Min, "A Comprarative Study of Velocity Overshoot Effect for Advanced MOSFET's Structures in Sub-0.1 m Regime", 제5회 한국 반도체 학술대회, pp. 71-72, Feb. 1998.

6. 신형순, 송두헌, 이경호, "A Comprehensive Model for Alpha-Particle-Induced Charge Collection", 제6회 한국 반도체 학술대회, pp. 139-140, Feb. 1999.

7. 홍성준, 나현철, 이찬호, 신형순, 박영준, 민홍식, "Analysis of the Accuracy of the Local  Thermal Noise Sources for the Impedance Field Method using the Monte Carlo Method", 제8회 한국 반도체 학술대회, pp. 5-6, 2001년 2월.

8. 류충렬, 이찬호, 신형순, 박영준, 민홍식, "A Novel Discretization Scheme combining both the Finite Element Method and the Box Integration Method", 제8회 한국 반도체 학술대회, pp. 9-10, 2001년 2월.

9. 이성원, 신형순, "A Study on the Validity of C-V Method for Extracting the Effective Channel Length of MOSFET", 제8회 한국 반도체 학술대회, pp. 11-12, 2001년 2월.

10. 김종철, 홍성준, 이찬호, 신형순, 박영준, 민홍식, "전자-전자 산란을 고려한 실리콘 소자에서의 몬테칼로 계산법", 제8회 한국 반도체 학술대회, pp. 13-14, 2001년 2월.

11. 나현철, 이찬호, 신형순, 박영준, 민홍식, "Characterization of the Generation-Recombination Noise under the Trap Assisted Condition using a 2-D Device Simulator", 제8회 한국 반도체 학술대회, pp. 263-264, 2001년 2월.

12. 이규일, 김진수, 신형순, 이찬호, 박영준, 민홍식, "A Simple Frequency-Domain Analysis of MOSFET Operation - Including Non-Quasistatic Effect", 제8회 한국 반도체 학술대회, pp. 275-276, 2001년 2월.

13. 선우경, 신형순, "A New Method to Extract the Lateral Profile of Hot-Carrier-Induced Nit using Charge Pumping Method", 제8회 한국 반도체 학술대회, pp. 279-280, 2001년 2월.

14. 이혁재, 신형순, 강대관, 박영준, 민홍식, "Reduction of Reverse Short Channel Effect in High-Energy Implanted Retrograde Well", 제8회 한국 반도체 학술대회, pp. 557-558, 2001년 2월.

15. 이혁재, 이종호, 신형순, 선우경, 강대관, 박영준, 민홍식, "Effects of STI on SOI Devices for Mixed Signal Processing", 제8회 한국 반도체 학술대회, pp. 559-560, 2001년 2월.

16. 이근정, 박지선, 신형순,  "Poly-Depletion and Quantum Effects in PMOSFET", 제9회 한국 반도체 학술대회, pp. 581-582, 2002년 2월.

17. 나현철, 이찬호, 신형순, 박영준, 민홍식, "Investigation of Noise Characteristics of p-n Diodes using Device Simulator", 제9회 한국 반도체 학술대회, pp. 47-48, 2002년 2월.

18. 김지현, 신형순, 이승준, "A Macro-Model and Sensing Circuit for MRAM", 제9회 한국 반도체 학술대회, pp. 577-578, 2002년 2월.

19. 김종철, 박태정, 홍성준, 김진수, 신형순, 이찬호, 박영준, 민홍식, "Electron-Electron Scattering and its Effects on Electron Transport in Silicon", 제9회 한국 반도체 학술대회, pp. 571-572, 2002년 2월.

20. 이지영, 신형순, “Evanescent-Mode Analysis of Short-Channel Effects in MOSFETs", 제10회 한국 반도체 학술대회, pp. 17-18, 2003년 2월.

21. 장은정, 이승준, 신형순, “A Sensing Circuit for MRAM based on 2MTJ-1T Structure", 제10회 한국 반도체 학술대회, pp. 281-282, 2003년 2월.

22. 이혜림, 신형순, “Analysis of Anomalous Subthreshold Characteristics in Lightly-Doped Asymmetric Double-Gate MOSFETs", 제10회 한국 반도체 학술대회, pp. 313-314, 2003년 2월.

23. 이규일, 이찬호, 신형순, 박영준, 민홍식, “An Efficient Method for Frequency-domain Simulation of Short Channel MOSFET Including the Non-Quasistatic Effect", 제10회 한국 반도체 학술대회, pp. 737-738, 2003년 2월

24. 박지선, 신형순, “폴리게이트의 양자 효과에 따른 Double-Gate MOSFET의 단채널 효과 분석”, 대한전자공학회 하계종합학술대회, pp. 691-694, 2003년 7월.

25. 이지영, 신형순, 진성훈, 박영준, 민홍식, “A Unified Mobility Model for MOS Inversion and Accumulation Layers with Quantum Mechanical Effect", 제11회 한국 반도체 학술대회, pp. 193-194, 2004년 2월.

26. 이승연, 김혜진, 이승준, 신형순, 김대정, “Midpoint-Reference Generation Circuit for MRAM", 제11회 한국 반도체 학술대회, pp. 467-468, 2004년 2월.

27. 한영모, 신형순, 성원용, “Galois 필드상의 효율적인 지수 연산을 위한 VLSI 구조”, 대한전자공학회 하계종합학술대회, pp. 1537-1540, 2004년 7월.

28. 이상경, 이승준, 신형순, “Analysis of the Charge Pumping Characteristics for Thin Gate Oxide in the Direct Tunneling Regime", 제12회 한국 반도체 학술대회, pp. 69-70, 2005년 2월.

29. 박지선, 이승준, 신형순, “Charge-based Analytical Current Model for Asymmetric Double-Gate MOSFETs", 제12회 한국 반도체 학술대회, pp. 71-72, 2005년 2월.

30. 이승연, 김지현, 이감영, 양희정, 이승준, 신형순, "Design of Single Bit Accumulator Using Magnetic-Tunnel-Junction Elements as Versatile Logic Components", 제 14회 한국반도체학술대회, pp. 1099-1100, 2007년 2월.

31. 이현주, 김소정, 이승연, 이승준, 신형순, “Magnetic-Tunnel-Junction Emulation Cell을 이용한 자기논리 회로 검증” 제16회 한국 반도체 학술대회, p. 454-455, 2009년 2월.

32. 박연희, 이승준, 신형순, “Synthesis of Nonvolatile Magnetologic Block Using MTJ-based Logic Modules”, 제17회 한국 반도체 학술대회, 2010년 2월.

33. 안소라, 임혜인, 서수만, 이경진, 신형순, 이승준, “Analytic Model of Spin-Torque Oscillators (STO) for Circuit-Level Simulation”, 제19회 한국 반도체 학술대회, 2012년 2월.

34. 안소라, 김지아, 신형순, 이승준, “Area-efficient a-Si Gate Driver Circuit with Shared Driving Node”, 제20회 한국 반도체 학술대회, 2013년 2월.

35. 김미련, 임혜인, 안소라, 이승준, 신형순, “Advanced Circuit-Level Model of Magnetic Tunnel Junction-based Spin-Torque Oscillator with Perpendicular Anisotropy Field”, 제20회 한국 반도체 학술대회, 2013년 2월.

36. 선우경, 최수진, 신형순, “Substrate Doping Concentration Dependence of Electron Mobility Enhancement in Uniaxial Strained (110)/<110> nMOSFETs”, 제21회 한국 반도체 학술대회, 2014년 2월.

37. 최수진, 선우경, 이인재, 신형순, “Analysis of Stress Effect on (110)-oriented Single Gate SOI nMOSFETs using Silicon-Thickness-Dependent Deformation Potential”, 제22회 한국 반도체 학술대회, 2015년 2월.

38. 임혜인, 선우경, 이우태, 신형순, “ReRAM Crossbar Array: Reduction of Access Time by Reducing Parasitic Capacitance of Selector Device”, 제22회 한국 반도체 학술대회, 2015년 2월.

39. 최수진, 선우경, 신형순, “A guideline for Electron Mobility Enhancement in uniaxially-strained (100)/<100> and (110)/<110> FinFETs”, 제23회 한국 반도체 학술대회, 2016년 2월.

40. 이인재, 김미련, 신민호, 신형순, “A new method for determination of subgap density of states in n/p-type LTPS TFTs”, 제23회 한국 반도체 학술대회, 2016년 2월.

41. 선우경, 최수진, 신형순, “Read Margin Analysis of Crossbar Array using Cell-Variability-Aware Simulation Method”, 제24회 한국 반도체 학술대회, 2017년 2월.

42. 최수진, 선우경, 신형순, “New modeling method for the dielectric relaxation of a DRAM cell capacitor”, 제24회 한국 반도체 학술대회, 2017년 2월.

43. 김영민, 조성재, 신형순, 박병국, “Design and Operation of Capacitorless Si Volatile Memory Based on 2-Terminal Thyristor (2-T TRAM)”, 제24회 한국 반도체 학술대회, 2017년 2월.

44. 김보경, 조수민, 선우경, 신형순, “Analysis of the Memristor-Based Cross-Bar Synapse for Neuromorphic System”, 제25회 한국 반도체 학술대회, 2018년 2월.

45. 정영현, 강인만, 선우경, 신형순, 조성재, “Tunneling Field-Effect Transistor Having SiGe Source Junction and Its Small-Signal Equivalent Circuit Verification through Y-Parameter Analysis”, 제25회 한국 반도체 학술대회, 2018년 2월.

46. 김현정, 선우경. 강인만, 조성재, 신형순, “Performance comparison between Conventional and Junctionless transistors as 1 T-DRAM cell with Poly-Silicon body”, 제26회 한국 반도체 학술대회, 2019년 2월.

47. 정용진, 박지선, 강인만, 조성재, 신형순, “Charge based Current-Voltage Model for the SOI-Junctionless FET”, 제26회 한국 반도체 학술대회, 2019년 2월.

48. 최수진, 선우경, 김보경, 신형순, “3D vertical RRAM (VRRAM) synapse for Neural Network system”, 제26회 한국 반도체 학술대회, 2019년 2월.

49. 최윤영, 박지선, 김미련, 신형순, “Analysis of OLED SPICE Models with Constant or Voltage-Dependent Components”, 제26회 한국 반도체 학술대회, 2019년 2월.

50. 유송이, 김현정, 강인만, 조성재, 선우경, 신형순, “Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si 1T_DRAM”, 제27회 한국 반도체 학술대회, 2020년 2월.

51. 최서연, 김다영, 선우경, 신형순, “A multi-Pulse Width based Memristive PUF (PWM-PUF) and Circuit Implementation”, 제27회 한국 반도체 학술대회, 2020년 2월.

52. 최윤영, 박지선, 이택영, 신형순, “Analysis of Transient Body Effect Model for LTPS TFT on Plastic Substrate”, 제27회 한국 반도체 학술대회, 2020년 2월.

53. 유송이, 하예진, 선우경, 신형순, “수평 방향 Grain boundary의 위치에 따른 Poly-Si 1T-DRAM의 메모리 성능”, 2020 대한전자공학회 하계학술대회, 2020년 8월.

54. 최서연, 김다영, 최윤영, 이정원, 선우경, 신형순, “전압 센스 앰프를 이용한 멤리스터 기반 물리적 복제 방지 하드웨어 개발”, 2020 대한전자공학회 하계학술대회, 2020년 8월.

55. 최윤영, 박지선, 신형순, “Flexible a-IGZO TFT 소자의 Tensile Stress에 따른 Sub-gap DOS 분석”, 2020 대한전자공학회 하계학술대회, 2020년 8월.

56. 하예진, 유송이, 선우경, 박지선, 신형순, “Transient Charateristics of Poly-Si 1T-DRAM Depending on the Channel Legth and Doping Concentration”, 제28회 반도체학술대회, p. 471, 2021년 1월.

57. 최윤영, 박지선, 신형순, “The Analysis of Band-gap State of Tensile Strained a-IGZO TFT Dependent on the Banding Direction and Channel Length”, 제28회 반도체학술대회, pp. 174-175, 2021년 1월.

58. 김다영., 최윤영, 이정원, 선우경, 신형순, “다중 비트 리스폰스를 생성하기 위한 멤리스터 Multi-Array 기반 Physical Unclonable Function (MA-PUF) 구현”, 2021 대한전자공학회 하계학술대회, 2021년 7월.

59. 하예진, 선우경, 박지선, 신형순, “Poly-Si 1T-DRAM의 Array 구조에서의 Disturbance 특성 분석”, 2021 대한전자공학회 하계학술대회, 2021년 7월.

60. 최윤영, 박지선, 신형순, “Strain 분포를 고려한 a-IGZO TFT의 DOS 분석”, 2021 대한전자공학회 하계학술대회, 2021년 7월.

61. 최윤영, 이정원, 신형순, 선우경, “PUF-to-PUF 인증방식”, 2022 대한전자공학회 하계학술대회, 2022년 6월.

Patent

1. A.F. Tasch, H. Shin, and C.M. Maziar, "Hot-Carrier Suppressed Sub-Micron MISFET Device", 1991 US PATENT 5012306.

2. A.F. Tasch, H. Shin, and C.M. Maziar, "Hot-Carrier Suppressed Sub-Micron MISFET Device", 1992 US PATENT 5093275.

3. A.F. Tasch, H. Shin, and C.M. Maziar, "Hot-Carrier Suppressed Sub-Micron MISFET Device", 1995 EU PATENT 5093275.

4. H. Shin, "Method of making Metal Oxide Semiconductor Field Effect Transistors with a Lightly Doped Drain Structure having a Recess Type Gate",1993 US PATENT 5270257.

5. 신형순, "MOS트랜지스터 제조방법", 1994 Korea Patent 073693.

6. 신형순, "리세스게이트를 갖는 반도체 장치의 제조 방법", 1994 Korea Patent 074565.

7. 신형순, "선택에피텍시를 이용한 반도체 소자의 제조 방법", 1994 Korea Patent 076438.

8. 신형순, "MOS 트랜지스터 제조방법",1994 Korea Patent 076439

9. 신형순, 김영관, "모스트랜지스터 제조방법",1996 Korea Patent 096479.

10. H. Shin, "Verfahren zur Herstellung von Metall-Oxid-Halbleiter-Feldeffekttransistoren", 1996 German Patent 4212829.

11. H. Shin, "MOS-FET-Struktur und Verfahren zu deren Herstellung", 1997 German Patent 4208537.

12. H. Shin, "Method for Manufacturing MOSFET",1998 Japan Patent 2826924.

13. H. Shin, "Method of making LDD Structure Spaced from Channel Doped Region",1999 US Patent 5904530.

14. 신형순, 송두헌, "반도체소자 및 그의 제조방법", 2001 Korea Patent 10-0287886.

15. 석중현, 유인경, 박상진, 신형순, "자성체 메모리 소자 및 그 동작방법", 2001 Korea Patent 10-0421215.

16. W. Park, H. Shin, S. Lee, "MRAM including unit cell formed of one transistor and two magnetic tunnel junctions (MTJS) and method for fabricating the same", 2005 US PATENT 6924520.

17. 박완준, 김태완, 박상진, 김대정, 이승준, 신형순, “자기 램 및 그 읽기 방법”, 2005 Korea Patent 10-0528341.

18. 김태완, 김기원, 신형순, 이승준, 황인준, 조영진, “자기터널접합 셀을 이용한 배타적 논리합 논리회로 및 상기 논리회로의 구동 방법”, 2007 Korea Patent 10-0682967.

19. W. Park, H. Shin, S. Lee, "MRAM including unit cell formed of one transistor and two magnetic tunnel junctions (MTJS) and method for fabricating the same", 2007 US PATENT 7195929.

20. 신형순, 원태영, “자기터널접합을 이용한 논리회로”, 2008 Korea Patent 10-0814108.

21. T. Kim, K. Kim, H. Shin, S. Lee, I. Hwang, and Y. Cho, “MAGNETIC TUNNELING JUNCTION BASED LOGIC CIRCUITS AND METHODS OF OPERATING THE SAME”,  2008 US PATENT 7439770.

22. 신형순, “자기 메모리 셀”, 2008 Korea Patent 10-0866973.

23. T. Kim, K. Kim, H. Shin, S. Lee, I. Hwang, and Y. Cho, “MAGNETIC TUNNELING JUNCTION BASED XOR LOGIC CIRCUITS AND METHODS OF OPERATING THE SAME”,  2009 EPO PATENT (DE, FR,GB) EP1826770.

24. 박완준, 신형순, 이승준, “단위 셀이 한 개의 트랜지스터와 두 개의 ＭＴＪ로 구성된 ＭＲＡＭ 및 그 제조방법”, 2009 Korea Patent 10-0923298.

25. 신형순, 이승연, 김지현, 이현주, 김소정, “스핀토크변환을 이용한 이중 자기터널접합 소자를 사용한 XOR 및 XNOR 논리연산장치", 2009 Korea Patent 10-0927195.

26. I. Hwang, H. Shin, S. Lee, S. Seo, K. Kim, and K. Kim, "SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME", 2010 US PATENT 7672154.

27. 신형순, 이승연, 이현주, 이감영, “스핀 토크 변환을 이용한 자기터널접합 소자를 사용한 XOR 논리 연산장치”, 2010 Korea Patent 10-0961723.

28. K. Kim, Y. Cho, H. Shin, S. Choa, S. Lee, and I. Hwang, "SEMICONDUCTOR MEMORY DEVICE AND MAGNETO-LOGIC CIRCUIT", 2010 US PATENT 7755930.

29. W. Park, T. Kim, S. Park, D. Kim, S. Lee, and H. Shin, “MAGNETIC RANDOM ACCESS MEMORY AND ITS DATA READ-OUT METHOD”, 2010 Japan Patent 4634153.

30. W. Park, T. Kim, S. Park, D. Kim, S. Lee, and H. Shin, “MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF READING DATA FROM THE SAME”, 2011 EPO PATENT (DE, FR,GB) EP1564750.

31. 신형순, 박성민, 정나래, 윤지숙, 김유진, “피드포워드 링 오실레이터”, 2011 Korea Patent 10-1064129.

32. 박성민, 신형순, 윤지숙, 정나래, 김유진, “다중 독립 게이트 전계-효과 트랜지스터를 이용한 피드포워드 제한 증폭기", 2011 Korea Patent 10-1070374.

33. S. Lee, H. Shin, S. Lee, S. Seo, Y. Cho, U. Pi, J. Bae, J. Heo, “MAGNETIC STORAGE DEVICE HAVING A BUFFER TRACK AND STORAGE TRACKS, AND METHOD OF OPERATING THE SAME”, 2011 US PATENT 8045371.

34. 신형순, 이승준, “불휘발성 메모리 장치 및 그것의 읽기 방법”, 2012 Korea Patent 10-1109555.

35. S. Lee, S. Seo, Y. Cho, J. Bae, U. Pi, H. Shin, S. Lee, “Information storage device and method of operating the same”, 2012 US PATENT 8144503.

36. K. Kim, S. Seo, K. Kim, I. Hwang, H. Shin, S. Lee, S. Lee, “Method of operating magnetic random access memory device”, 2012 US PATENT 8144504.

37. K. Kim, H. Shin, S. Lee, “Magnetic random access memories and methods of operating the same”, 2012 US PATENT 8194439.

38. Y. Cho, H. Shin, S. Lee, S. Seo, S. Lee, J. Bae, “Information storage devices using magnetic domain wall movement and methods of operating the same", 2012 US PATENT 8320152.

39. W. Park, T. Kim, S. Park, D. Kim, S. Lee, H. Shin, “Magnetic random access memory and method of reading data from the same", 2012 US PATENT 8320166.

40. T. Kim, K. Kim, H. Shin, S. Lee, I. Hwang, and Y. Cho, “MAGNETIC TUNNELING JUNCTION CELL BASED XOR LOGIC CIRCUIT AND METHOD OF OPERATING THE SAME”, 2013 JAPAN PATENT 5221043

41. H. Shin, "Magnetic Memory Cell", 2013 US PATENT 8542527.

42. 신형순, “자기저항 메모리”, 2013 Korea Patent 10-1325188.

43. S. Lee, H. Shin, S. Lee, S. Seo, Y. Cho, U. Pi, J. Bae, and J. Heo, “Information storage devices and methods of operating the same”, 2013 JAPAN PATENT 5345091.

44. 조영진, 신형순, 좌성훈, 이승준, 김기원, 황인준, “ＭＴＪ(Ｍａｇｎｅｔｉｃ Ｔｕｎｎｅｌ Ｊｕｎｃｔｉｏｎ)을 이용하는 카운터 논리 회로”, 2013 Korea Patent 10-1334179.

45. 김기원, 조영진, 신형순, 좌성훈, 이승준, 황인준, “반도체 메모리 장치 및 마그네토 논리 회로”, 2013 Korea Patent 10-1334180.

46. 황인준, 신형순, 이승준, 서순애, 김기원, 김광석, “필드 프로그래머블 반도체 메모리장치 및 그 프로그래밍방법", 2013 Korea Patent 10-1334184.

47. 김기원, 신형순, 좌성훈, 이승준, 조영진, 황인준, “ＭＴＪ(Ｍａｇｎｅｔｉｃ Ｔｕｎｎｅｌ Ｊｕｎｃｔｉｏｎ)을 이용하는 가산기 논리 회로”, 2014 Korea Patent 10-1367280.

48. S. Lee, S. Seo, Y. Cho, J. Bae, U. Pi, H. Shin, and S. Lee, “Information storage device and method of operating the same”, 2014 JAPAN PATENT 5478238.

49. K. Kim, S. Seo, K. Kim, I. Hwang, H. Shin, S. Lee, and S. Lee, "Method of operating Magnetic random access memory device", 2014 CHINA PATENT 101625890.

50. H. Shin, S. Park, N. Jeong, J. Yun, and Y. Kim, “Feed-Forward Ring Oscillator” 2014  US PATENT 8742855.

51. Y. Cho, H. Shin, S. Lee, S. Seo, S. Lee, J. Bae, “Information storage devices using magnetic domain wall movement and methods of operating the same", 2014 JAPAN PATENT 5520531.

52. S. Lee, S. Seo, Y. Cho, J. Bae, U. Pi, H. Shin, and S. Lee, “Information storage device and method of operating the same”, 2014  CHINA PATENT 101763889.

53. Y. Cho, H. Shin, S. Lee, S. Seo, S. Lee, J. Bae, “Information storage devices using magnetic domain wall movement and methods of operating the same", 2014  CHINA PATENT 101635166.

54. 조영진, 신형순, 이승준, 서순애, 이성철, 배지영, “자구벽 이동을 이용한 정보저장장치 및 그 동작방법”, 2014 Korea Patent 10-1466237.

55. 신형순, “자기 저항 메모리”, 2015 Korea Patent 10-1488939

56. 김광석, 서순애, 김기원, 황인준, 신형순, 이승준, 이승연, “자기 메모리 소자의 구동 방법”, 2015 Korea Patent 10-1493868

57. H. Shin, “Magnetic Random Access Memory", 2015 US PATENT 9135959.

58. 김광석, 신형순, 이승준, “자기 메모리 및 그 동작 방법”, 2016 Korea Patent 10-1604042.

59. 신형순, 선우경, “저항성 메모리 장치 및 그 구동 방법”, 2016 Korea Patent  10-1654135.

60. 신형순, 선우경, 조수민, 박준희, “뉴로 모픽 소자 및 이를 이용한 가이드 트레이닝 방법”, 2019년 11월 한국특허 10-2049463.

61. 조성재, 신형순, “핀펫 구조를 갖는 폴리실리콘 기반의 1T 디램 셀 소자 및 그 제조방법”, 2019년 11월 한국특허 10-2051306.

62. 조성재, 신형순, “폴리실시콘기반의 1T 디램 셀소자 및 그 제조방법”, 2019년 11월 한국특허 10-2051304.

63. 신형순, 선우경, 조수민, “3차원 크로스바 메모리 구조를 이용한 뉴로모픽소자”, 2020년 5월 18일 한국특허 10-2114356.

64. 신형순, 선우경, “3차원 크로스바 메모리 구조를 이용한 뉴로모픽소자”, 2020년 6월 4일 한국특허 10-2121562

65. S. Cho and H. Shin, “One-transistor dram cell device based on polycrystalline silicon withFinFET structure and fabrication method thereof”, 2020년 7월 14일 US PATENT 10714479.

66. 신형순, 선우경, 권효진, 김다영, “3차원 크로스바 메모리를 이용한 난수 발생 장치”, 2020년 8월 25일 한국특허 10-2150003

67. 신형순, 김다영, 선우경, 이정원, 최서연, “물리적 복제 방지 기능을 가진 난수 발생 장치”, 2021년 4월 26일 한국특허 10-2246513

68. 신형순, 김다영, 선우경, 이정원, 최서연, 최윤영, “복수의 PUF 칩들을 포함하는 인증장치”, 2021년 7월 22일 한국특허 10-2282855

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