The use of reconfigurable chips in High-Performance Computers (HPC) offers more efficient scalable devices. At the same time, it may also introduce some challenges, such as overhead. Our work focuses on overcoming those challenges. Some of our previous works are presented below.
High-Performance Reconfigurable Computers (HPRC) are parallel computing systems that contain multiple microprocessors and multiple FPGAs. Their design uses FPGAs as coprocessors that are deployed to execute the small portion of the application that takes most of the time. These systems have the potential to exploit coarse-grained functional parallelism as well as fine-grained instruction-level parallelism through direct hardware execution on FPGAs. The research on HPRCs revealed that they can provide a significant order of magnitude improvement in performance. It also reduces power consumption and saves cost and size requirements compared to contemporary microprocessors when executing compute-intensive applications. Click here to read the reference article.
Classification of modern HPRCs (a) uniform node nonuniform systems (UNNSs) and (b) nonuniform node uniform systems (NNUSs)
Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of HPRCs. However, the RTR feature comes with the cost of some configuration overhead. One limitation of reconfigurable computing is that some large applications require more hardware resources than are available, and the complete design cannot fit in a single FPGA chip. One solution to this problem is Full Runtime Reconfiguration (FRTR). Recent generations of FPGAs support Partial Runtime Reconfiguration (PRTR) where application modules can be dynamically uploaded and deleted from the FPGA chip without affecting other running modules. The reconfiguration time introduces a significant overhead for FRTR because most existing FPGAs use relatively slow interfaces for device configuration. Since the configuration time could be significant, eliminating or reducing this overhead becomes an important area of research. Click here to read the reference article.
Partial reconfiguration arrangement for some contemporary Xilinx devices
