Invited Spearkers

Invited Speakers

Prof. Kurt Keutzer

Professor at UC Berkeley

Kurt’s research at UC Berkeley focuses on making the training and inference of Deep Neural Networks more computationally efficient. Kurt’s collaborations on Neural Network training have scaled that problem to 2000 processors and reduced the training time on the ImageNet dataset to minutes. Kurt’s collaborations in Neural Network design have produced SqueezeNet and a related family of small energy-efficient Neural Networks that reduced the memory footprint and energy-consumption of Convolutional Neural Networks.

Forrest Iandola

CEO at DeepScale

Forrest Iandola completed a PhD in EECS at UC Berkeley, where his research focused on improving the efficiency of deep neural networks. His advances in scalable training and efficient implementation of DNNs led to the founding of DeepScale, where he is CEO. DeepScale builds vision/perception systems for automated vehicles.

Pete Warden

Staff Research Engineer at Google

Pete Warden is the tech lead of TensorFlow's Mobile and Embedded team, and was previously CTO of Jetpac, acquired by Google in 2014.

Prof. Ali Farhadi

Professor at University of Washington

I am an Assistant Professor in the Department of Computer Science & Engineering at the University of Washington. Before this, I spent a year as a postdoctoral fellow at the Robotics Institute at Carnegie Mellon University working with Martial Hebert and Alyosha Efros. I got my PhD from University of Illinois at Urbana-Champaign under the supervision of David Forsyth. During my PhD I also had the privilege of working closely with Derek Hoiem

Prof. Song Han

Assistant Professor at MIT

Song Han received the Ph.D. degree from Stanford University advised by Prof. Bill Dallyat Stanford University. His research focuses on energy-efficient deep learning, at the intersection between machine learning and computer architecture. He proposed Deep Compression that can compress deep neural networks by an order of magnitude without losing the prediction accuracy. He designed EIE: Efficient Inference Engine, a hardware architecture that can perform inference directly on the compressed sparse model, which saves memory bandwidth and results in significant speedup and energy saving. His work has been featured by TheNextPlatform, TechEmergence, Embedded Vision and O’Reilly. He led research efforts in model compression and hardware acceleration for deep learning that won the Best Paper Award at ICLR’16 and the Best Paper Award at FPGA’17. Before joining Stanford, Song graduated from Tsinghua University. I will join MIT EECS as an assistant professor starting summer 2018.

Jilei Hou

Head of AI Research Group, Qualcomm Research

Lead the center of excellence in the area of AI/ML for Qualcomm; responsible for building the ML research infrastructure and core capabilities for the company; drive the ML research leadership and broaden the connection into academic community.

Panelists

Dr. Michael James

Cerebra’s Chief Architect

Cerebras builds systems that accelerate deep learning by three orders of magnitude over the best in class GPU (1-unit equivalent to 1000 Pascal Nvidia GPUs). The benefit to our customers is that the CS-1 reduces training time from months to hours, and from weeks to minutes. And when used for inference, the system reduces latency by 1,000 X. From milliseconds to microseconds. We achieve these goals without requiring any changes to the deep learning framework software. So, we ingest Tensorflow, Cafe, Torch, Theano without modification.

Dr. Dave Driggers

CEO Cirrascale

Cirrascale Corporation is a premier developer of hardware and cloud-based solutions enabling GPU-driven deep learning infrastructure. Cirrascale architects and deploys deep learning infrastructure for customers, as well as manages a GPU as a Service (GPUaaS) offering using hardware and software infrastructure optimized for Deep Learning algorithms enabling data scientists to focus on application development and optimization.

Naveen Kumar

Sr. Staff Engineer at Google

Naveen Kumar leads the Performance Architecture group of Tensor Processing Units at Google. His current research focuses on scalability techniques for Machine Learning applications. In addition, Naveen's research interests include parallel algorithms, workload characterization and hardware-software co-design. Prior to Google, Naveen focused on Microprocessor research at Intel Labs. Naveen holds a PhD in Computer Science from the University of Pittsburgh and has authored several dozen research papers and patents.

Prof. Dhabaleswar Panda

Ohio State University

Dr. Dhabaleswar K. (DK) Panda is a Professor and Distinguished Scholar of Computer Science at the Ohio State University. He obtained his Ph.D. in computer engineering from the University of Southern California. His research interests include parallel computer architecture, high performance networking, InfiniBand, network-based computing, exascale computing, programming models, GPUs and accelerators, high performance file systems and storage, virtualization and cloud computing and BigData (Hadoop (HDFS, MapReduce and HBase) and Memcached). He has published over 400 papers in major journals and international conferences related to these research areas. Dr. Panda has served (or serving) as Program Chair/Co-Chair/Vice Chair of many international conferences and workshops including CCGrid '18, ExaComm (15-17), ESPM2 (15-17), HPBDC (15-18), CCGrid '16, PGAS '15, HPBDC '15, HiPC '12, CCGrid '12, HiPC '11, IEEE Cluster (Cluster)'10, Supercomputing (SC)'08, ANCS '07, Hot Interconnect 2007, IPDPS '07, HiPC '07, Hot Interconnect 2006, CAC (2001-04), ICPP '01, CANPC (1997-98) and ICPP '98. He has served as the General Chair of ICPP '06. He has served as an Associate Editor of IEEE Transactions on Parallel and Distributed Systems (TPDS), IEEE Transactions on Computers (TC), and Journal of Parallel and Distributed Computing (JPDC). He has served as Program Committee Member for more than 100 international conferences and workshops. Prof. Panda is a motivated speaker. He has Served as an IEEE Distinguished Visitor and an IEEE Chapters Tutorial Speaker. He has delivered a large number of invited Keynote/Plenary Talks, Tutorials and Presentations Worldwide.