Syllabus

• Hardware modeling with the Verilog HDL. Encapsulation, modeling primitives, different types of description.

• Logic system, data types and operators for modeling in Verilog HDL. Verilog Models of propagation delay and net delay path delays and simulation, inertial delay effects and pulse rejection. Delay simulation in Verilog and FPGA implementation.

• Behavioral descriptions in Verilog HDL. Synthesis of combinational logic. FPGA Implementation.

• HDL-based synthesis - technology-independent design, styles for synthesis of combinational and sequential logic, synthesis of finite state machines on FPGA, synthesis of gated clocks, design partitions and hierarchical structures.

• Synthesis of language constructs, nets, register variables, expressions and operators, assignments and compiler directives. Switch-level models in Verilog. Design examples in Verilog and Implementation on FPGA.

References

[1] M. D. Ciletti, Advanced Digital Design with the Verilog HDL, 2nd ed. Pearson, 2010.
[2] S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2nd ed. Pearson, 2003.
[3] J. Bhaskar, A Verilog HDL Primer, 3rd ed. Springer, 2022.
[4] M. G. Arnold, Verilog Digital Computer Design: Algorithms into Hardware, Prentice Hall PTR, 1999.