1. Code converters, Carry Skip Adder 

2. Comparator, Mux, Demux, Priority Encoder

3. Flip Flops, Universal Shift Register, Up/Down Counter

4. Array Multiplier, ALU

5. Mealy, Moore FSMs

6. Three Tap FIR, RAM

7. Synchronous FIFO

8. Project Demonstration and Presentation 

Last Year's Project Topics

1. Hybrid Recursive Karatsuba Multiplier Using Dadda Multiplier Architecture

2. Accelerating Automatic Target Recognition Using Extreme Hardware Parallelism (WIDER Architecture)

3. Efficient Critical Path CVLCG-Based Pseudorandom Bit Generator

4. Low-Power RTL Architecture for a Pipelined Distance-Based Machine Learning Classifier

5. Multi-Lane Hybrid Merge Sort Accelerator for FPGA

6. Hardware Reduction for Finite State Machines (FSMs) Using Extended State Coding with Automated Class Partitioning

7. Optimized MAC Unit Using Counter-Based Wallace Tree Multiplier with Pipelining

8. Processing-in-Memory (PIM) Controller Design

9. In-Memory Computation Using an SRAM-Based CAM-Driven Associative Processor Architecture

10. Content-Aware Variable Latency Divider with Single-Cycle Bypass Logic

Suggested Project Areas

1. Digital Arithmetic Architectures (Adders, Multipliers, Dividers, ALU, MAC Units)

2. RTL Optimization Techniques (Area, Power, Delay, and Pipelining)

3. FSM-Based Digital System Design (Controllers and Communication Protocols)

4. Memory and Buffer Architectures (FIFO, RAM, Cache, Memory Controllers)

5. DSP and Signal Processing Modules (FIR Filter, FFT, CORDIC, Digital Filters)