Embedded Files
1. Text book
Computer Organization and Architecture, 9th Edition
2. References
Computer Organization and Design, 5th Edition
3. Schedule
4. Syllabus
Part 1: Overview
Chapter 1 Introduction
1.1 Organization and Architecture
1.2 Structure and Function
Chapter 2 Computer Evolution and Performance
2.1 A Brief History of Computers
2.2 Designing for Performance
2.3 Multicore, MICs, và GPGPUs
2.4 The Evolution of the Intel x86 Architecture
2.5 Embedded Systems and the ARM
2.6. Performance Assessment
Part 2: The Computer System
Chapter 3 A Top-Level View of Computer Function and Interconnection
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
3.5 Point-To-Point Interconnect
3.6 PCI Express
Chapter 4 Cache Memory
4.1 Computer Memory System Overview
4.2 Cache Memory Principles
4.3 Elements of Cache Design
4.4 Pentium 4 Cache Organization
4.5 ARM Cache Organization
Chapter 5 Internal Memory
5.1 Semiconductor Main Memory
5.2 Error Correction
5.3 Advanced Dram Organization
Chapter 6 External Memory
6.1 Magnetic Disk
6.2 RAID
6.3 Solid State Drives
6.4 Optical Memory
6.5 Magnetic Tape
Chapter 7 Input/Output
7.1 External Devices
7.2 I/O Modules
7.3 Programmed I/O
7.4 Interrupt-Driven I/O
7.5 Direct Memory Access
7.6 I/O Channels and Processors
Part 3: Arithmetic and Logic
Chapter 9 Number Systems
8.1 The Decimal System
8.2 Positional Number Systems
8.3 The Binary System
8.4 Converting Between Binary and Decimal
8.5 Hexadecimal Notation
Chapter 10 Computer Arithmetic
9.1 The Arithmetic and Logic Unit
9.2 Integer Representation
9.3 Integer Arithmetic
9.4 Floating-Point Representation
9.5 Floating-Point Arithmetic
Part 4: The Central Processing Unit
Chapter 12 Instruction Sets: Characteristics and Functions
10.1 Machine Instruction Characteristics
10.2 Types of Operands
10.3 Intel x86 and ARM Data Types
10.4 Types of Operations
10.5 Intel x86 and ARM Operation Types
Chapter 13 Instruction Sets: Addressing Modes and Formats
11.1 Addressing Modes
11.2 x86 and ARM Addressing Modes
11.3 Instruction Formats
11.4 x86 and ARM Instruction Formats
11.5 Assembly Language
Chapter 14 Processor Structure and Function
12.1 Processor Organization
12.2 Register Organization
12.3 Instruction Cycle
12.4 Instruction Pipelining
12.5 The x86 Processor Family
12.6 The ARM Processor
5. Further Reading
Chapter 8 Operating System Support
8.1 Operating System Overview
8.2 Scheduling
8.3 Memory Management
8.4 Pentium Memory Management
8.5 ARM Memory Management
Chapter 11 Digital Logic 364
11.1 Boolean Algebra
11.2 Gates
11.3 Combinational Circuits
11.4 Sequential Circuits
11.5 Programmable Logic Devices
Chapter 15 Reduced Instruction Set Computers
15.1 Instruction Execution Characteristics
15.2 The Use of a Large Register File
15.3 Compiler-Based Register Optimization
15.4 Reduced Instruction Set Architecture
15.5 RISC Pipelining
15.6 MIPS R4000
15.7 Sparc 562
15.8 RISC Versus CISC Controversy
Chapter 16 Instruction-Level Parallelism and Superscalar Processors
16.1 Overview
16.2 Design Issues
16.3 Pentium 4
16.4 Arm Cortex-A8
Chapter 17 Parallel Processing
17.1 Multiple Processor Organizations
17.2 Symmetric Multiprocessors
17.3 Cache Coherence and the MESI Protocol
17.4 Multithreading and Chip Multiprocessors
17.5 Clusters
17.6 Nonuniform Memory Access
17.7 Vector Computation
Chapter 18 Multicore Computers
18.1 Hardware Performance Issues
18.2 Software Performance Issues
18.3 Multicore Organization
18.4 Intel x86 Multicore Organization
18.5 ARM11 MPCore
18.6 IBM zEnterprise 196 Mainframe
5. Other Resources
6. Evaluation
1. Progress (Attendance + Discussion + Assignment/Project + Midterm Test): 40%
2. Final Exam (Objective Test, In English): 60%
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