Lab 5

Project 5 : DAC Siren

Step 1: Upload dac_if.vhd Source Code

This code is necessary in order to properly utilize the digital to analog converter we will be using to output our signal.

In this code the SREG is used to serially shift data out to DAC, MSBit first. Left data is loaded into SREG on falling edge of SCLK when L_start is active. Right data is loaded into SREG on falling edge of SCLK when R_start is active. At other times, falling edge of SCLK causes REG to logically shift one bit left Serial data to DAC is MSBit of SREG.

Step 2A: Upload siren.vhd Source Code

In this code the process sets up a 20 bit binary counter clocked at 50MHz. This is used to generate all necessary timing signals. dac_load_L and dac_load_R are pulses sent to dac_if to load parallel data into shift register for serial clocking out to DAC

Step 2B: Upload siren.xdc Constraint Code

This constraint code is required to properly set the clock sped of our device.

Step 3: Upload tone.vhd Source Code

This source code generates a 16-bit signed triangle wave sequence at a sampling rate determined by input clk and with a frequency of (clk*pitch)/65,536

Step 4: Upload wail.vhd Source Code

This code generates a "wailing siren" sound by instancing a "tone" module and modulating the pitch of the tone. The pitch is increased until it reaches hi_pitch and then decreased until it reaches lo_pitch and then increased again...etc.