List of Publications

3.  B. Jajodia, A. Mahanta and R. A. Shaik, "Energy-Efficient DAC Switching Technique for Single-Ended SAR ADCs", AEU - International Journal of Electronics and Communications, Elsevier, Vol. 124, 153334, September 2020, doi: https://doi.org/10.1016/j.aeue.2020.153334

2.  B. Jajodia, A. Mahanta and R. A. Shaik, "IEEE 802.15.6 WBAN Standard Compliant IR-UWB Time-Hopping PPM Transmitter using SRRC signaling pulse”, AEU - International Journal of Electronics and Communications, Elsevier, Vol. 117, 153119, April, 2020, doi: https://doi.org/10.1016/j.aeue.2020.153119

1.  B. Jajodia, A. Mahanta and R. A. Shaik, "Mixed-Signal Demodulator for IEEE 802.15.6 IR-UWB WBAN Energy Detection based Receiver", IET Circuits, Devices & Systems, Vol 12 (5), 2018, pp. 523-531, doi: https://doi.org/10.1049/iet-cds.2017.0350

Book Chapters

2.  S. Jakhodia, D. Singh and B. Jajodia, “Experimental Evaluation of QFT Adders on IBM QX Hardware”, 2nd International Conference on Emerging Technologies for Computing, Communication and Smart Cities (ETCCS), Virtual Mode, Springer, 21-22 August, 2021 , In: Singh, P.K., Kolekar, M.H., Tanwar, S., Wierzchoń, S.T., Bhatnagar, R.K. (eds) 2nd International Conference on Emerging Technologies for Computing, Communication and Smart Cities (ETCCS), Lecture Notes in Electrical Engineering, vol. 875, pp. 419-435, Springer, Singapore, 20th April 2022, Print ISBN: 978-981-19-0283-3, Online ISBN: 978-981-19-0284-0, 2022, doi: https://doi.org/10.1007/978-981-19-0284-0_31

1.  D. Singh, S. Jakhodia and B. Jajodia, “Experimental Evaluation of Adder Circuits on IBM QX Hardware”, in 3rd International Conference on Inventive Computation and Information Technologies (ICICIT), Virtual Mode, Springer, 12-13 August, 2021, In: Smys S., Balas V.E., Palanisamy R. (eds) Inventive Computation and Information Technologies (ICICIT). Lecture Notes in Networks and Systems, vol. 336. pp. 333-347, Springer, Singapore, 01st January 2022, Print ISBN: 978-981-16-6722-0, Online ISBN: 978-981-16-6723-7, 2022, doi; https://doi.org/10.1007/978-981-16-6723-7_25

International/National Conferences

29. R. Maharana, A. Roy, S. K. Singh, M. Das and B. Jajodia, “FPGA-Optimized Seven-Term Karatsuba Multipliers for Large Integer Arithmetic”, in 2024 First IEEE International Conference on Electronics, Communication and Signal Processing  (ICECSP), Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Delhi, Delhi, 8-10 August, 2024 (Accepted)

28. S. Kumar, S. Patel, S. Singh, M. Das and B. Jajodia, “Design and Evaluation of FPGA-Optimized Asymmetrical Three-Term Karatsuba Multipliers”, in 2024 First IEEE International Conference on Electronics, Communication and Signal Processing  (ICECSP), Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Delhi, Delhi, 8-10 August, 2024 (Accepted)

27. S. Patel, S. Singh, S. Kumar, M. Das and B. Jajodia, “ATP-Optimized Four-Term Karatsuba Multipliers for Large Integer Arithmetic on FPGAs”, in 2024 First IEEE International Conference on Electronics, Communication and Signal Processing  (ICECSP), Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Delhi, Delhi, 8-10 August, 2024 (Accepted)

26. R. Maharana, S. K. Singh, A. Roy, M. Das and B. Jajodia, “FPGA-Optimized Asymmetrical and Symmetrical Six-Term Karatsuba Multipliers”, in 2024 First IEEE International Conference on Electronics, Communication and Signal Processing  (ICECSP), Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Delhi, Delhi, 8-10 August, 2024 (Accepted)

25. R. Maharana, M. Das and B. Jajodia, “Design and Evaluation of FPGA-Optimized Asymmetrical and Symmetrical Five-Term Karatsuba Multipliers”, in 2024 3rd IEEE International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE),  Dhaka University of Engineering & Technology (DUET), Gazipur, Bangladesh, 25-27 April, 2024 (Accepted and Presented)

24. S. Singh, S. Patel, S. Kumar, M. Das and B. Jajodia, “An Eight-Term Karatsuba Multiplier for Cryptographic Hardware Primitives on FPGAs”, in 2024 3rd IEEE International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE),  Dhaka University of Engineering & Technology (DUET), Gazipur, Bangladesh, 25-27 April, 2024 (Accepted and Presented)

23.  J. Lalwani, D. Linnet, B. Jajodia, M. B. Pande, A. Patel, K. Dave and B R Nikilesh, "Efficient Earth Observation Satellites Mission Planning with Quantum Algorithm", in 2024 Second IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies (TQCEBT), Christ (Deemed to be University), Pune Lavasa Campus, Pune, India, 22-23 March, 2024 (Accepted and Presented)

22.  S. Kumar, S. Patel, S. Singh, M. Das and B. Jajodia, “FPGA-Optimized Two-Term Karatsuba Multiplications for Large Integer Multiplications”, in 2024 11th IEEE International Conference on Signal Processing and Integrated Networks (SPIN),  ASET, Amity University, Sec-125, Noida, Delhi-NCR, India, 21-22 March, 2024, doi:  https://doi.org/10.1109/SPIN60856.2024.10512164

21.  S. Kumar, S. Patel, S. Singh, M. Das and B. Jajodia, “Design and Evaluation of FPGA-Optimized Symmetrical Three-Term Karatsuba Multipliers”, in 2024 IEEE International Conference on Recent Innovation in Smart and Sustainable Technology (ICRISST), Presidency University, Itgalpura, Rajanukunte, Yelakhana, Bangalore, Karnataka,, India, 15-16 March, 2024 (Accepted and Presented)

20.  S. Singh, S. Patel, S. Kumar, M. Das and B. Jajodia, “FPGA-Optimized Eight-Term Karatsuba Multiplications for Large Integer Multiplications”, in 2024 IEEE International Conference on Recent Innovation in Smart and Sustainable Technology (ICRISST), Presidency University, Itgalpura, Rajanukunte, Yelakhana, Bangalore, Karnataka,, India, 15-16 March, 2024 (Accepted and Presented)

19.  M. Das and B. Jajodia, “FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives”, in 2022 19th IEEE International SoC Conference (ISOCC), Lakai Sandpine Resort, Gangneung-si, Gangwon-do, Korea, 19-20 October, 2022, pp. 81-82, doi: https://doi.org/10.1109/ISOCC56007.2022.10031517

18.  M. Das and B. Jajodia, “Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA”, in 2022 19th IEEE International SoC Conference (ISOCC), Lakai Sandpine Resort, Gangneung-si, Gangwon-do, Korea, 19-20 October, 2022, pp. 65-66, doi: https://doi.org/10.1109/ISOCC56007.2022.10031366

17.  M. Karthik, J. Lalwani and B. Jajodia, "Quantum Image Teleportation Protocol (QITP) and Quantum Audio Teleportation Protocol (QATP) by using Quantum Teleportation and Huffman Coding", in 2022 IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies (TQCEBT), Christ (Deemed to be University), Pune Lavasa Campus, Pune, India, 13-15 October, 2022, pp.1-6, doi: https://doi.org/10.1109/TQCEBT54229.2022.10041599

16.  A. Chandra, J. Lalwani and B. Jajodia, "Towards an Optimal Hybrid Algorithm for EV Charging Stations Placement using Quantum Annealing and Genetic Algorithms ", in 2022 IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies (TQCEBT), Christ (Deemed to be University), Pune Lavasa Campus, Pune, India, 13-15 October, 2022, pp.1-6, doi: https://doi.org/0.1109/TQCEBT54229.2022.10041464, (Preprint: ArXiv Quantum Physics (quant-ph); Neural and Evolutionary Computing, 2021, doi: https://arxiv.org/abs/2111.01622 )

15. M. Karthik, J. Lalwani and B. Jajodia, "Quantum Text Teleportation Protocol for Secure Text Transfer by using Quantum Teleportation and Huffman Coding ", in 2022 IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies (TQCEBT), Christ (Deemed to be University), Pune Lavasa Campus, Pune, India, 13-15 October, 2022, pp.1-6, doi: https://doi.org/10.1109/TQCEBT54229.2022.10041500  (Preprint:  OSF Preprints, 2022, doi: https://osf.io/4svxf/)

14. M. Thakare and B. Jajodia, “Hardware Implementation for Determining Perfect and Non-Perfect Square Roots using Dwandwa Yoga on FPGA”, in 2022 IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), Prague, Czech Republic, 20-22 July, 2022, pp.1-6, doi: https://doi.org/10.1109/ICECET55527.2022.9872778

13.  P. Das and B. Jajodia, ``Design Automation of Two-Stage Operational Amplifier Using Multi-Objective Genetic Algorithm and SPICE Framework," in 2022 IEEE 5th International Conference on Inventive Computation Technologies (ICICT), Lalitpur, Nepal, 20-22 July, 2022, pp. 166-170, https://doi.org/10.1109/ICICT54344.2022.9850461

12.  V. Mishra, D. Pandey, S. Singh, S. Satapathy,, K. Goswami, B. Jajodia and D.S. Banerjee, "ART-MAC: An Approximate Rounding and Truncation Based MAC Unit for Fault-Tolerant Applications", in 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, Texas, USA, 28 May-June 1, 2022, pp. 1640-1644, doi: https://doi.org/10.1109/ISCAS48785.2022.9937437

11.  S. Singh, V. Mishra, S. Satapathy, D. Pandey, K. Goswami, D.S. Banerjee and B. Jajodia, "EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification", in 2022  IEEE 23rd International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, USA, 6-8 April, 2022, pp. 1-7, https://doi.org/10.1109/ISQED54688.2022.9806220

10.  D. Pandey, V. Mishra, S. Singh, S. Satapathy, B. Jajodia and D.S. Banerjee, "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications", in 2022 IEEE 23rd International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, USA, 6-8 April, 2022, pp. 1-7, doi: https://doi.org/10.1109/ISQED54688.2022.9806249

9. P. Yash, M. Thakare and B. Jajodia, “Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA”, in 2022 IEEE 13th Latin American Symposium on Circuits and Systems (LASCAS),  Puerto Varas, Chile, 1-4 March, 2022, pp.1-4, doi: https://doi.org/10.1109/LASCAS53948.2022.9789063

8.  S. Jakhodia and B. Jajodia, “Numerical Methods for Solving High-Order Mathematical Problems Using Quantum Linear System Algorithm on IBM QISKit Platform”, in 2022  IEEE 3rd International Conference on Innovative Trends in Information Technology (ICITIIT), Virtual Mode, 12-13 February, 2022, pp. 1-7, doi: https://doi.org/10.1109/ICITIIT54346.2022.9744239

7.  J. Bajaj and B. Jajodia, “Efficient Hardware Implementation of High-Speed Recursive Vedic Squaring Architecture on FPGA”, in 2021 IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape Town, South Africa, 9-10 December, 2021, pp. 1-6, doi: https://doi.org/10.1109/ICECET52533.2021.9698774

6.  M. Thakare, P. Yash, D. Chakraborty and B. Jajodia, “Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA," in 2021 IEEE 64th International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 373-376, doi: https://doi.org/10.1109/MWSCAS47672.2021.9531843

5.  R. Thombre and B. Jajodia, “Experimental Analysis of Attacks on RSA & Rabin Cryptosystems using Quantum Shor’s Algorithm," in Proceedings of International Conference on Women Researchers in Electronics and Computing (WREC), AIJR Proceedings, April 22-24, 2021, pp. 581-590, doi: https://doi.org/10.21467/proceedings.114.74 (Best Paper Award)

4.  J. Bajaj and B. Jajodia, “Squaring Technique using Vedic Mathematics," in Proceedings of International Conference on Women Researchers in Electronics and Computing (WREC),  AIJR Proceedings, April 22–24, 2021, pp. 591-600,  doi: https://doi.org/10.21467/proceedings.114.75

3.  B. Jajodia, R. A. Shaik and A. Mahanta, “Demodulation Techniques for IEEE 802.15.6 IR-UWB DBPSK WBAN Transceivers," in 2015 IEEE International Conference on Smart Instrumentation, Measurement and Applications (ICSIMA), Putrajaya Marriott Hotel, Malaysia, 2015, pp.1-5, doi: https://10.1109/ICSIMA.2015.7559011

2.  B. Jajodia, R. A. Shaik and A. Mahanta, “PPM Demodulation Schemes for IEEE 802.15.6 IR-UWB WBAN Receivers," in 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES), 2015, pp.1-5, doi: https://doi.org/10.1109/SPICES.2015.7091558

1.  B. Jajodia, A. Mahanta, and R. A. Shaik, “A Six-Segment SRRC Pulse Generator for IEEE 802.15.6 WBAN Standard," in Proc. of the 9th International Conference on Body Area Networks, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), BodyNets 2014, Senate House, London, Great Britain, 2014, pp.46-49, doi: https://doi.org/10.4108/icst.bodynets.2014.257093

Posters

1. D. Pandey, V. Mishra, S. Singh, S. Satapathy and B. Jajodia, "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications", in 28th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) Student Research Symposium (SRS), Bengaluru, Karnataka, 17-18 December 2021 (Best Poster Award)

Others