B. Naresh Kumar Reddy graduated B.Tech in Electronics and Communication Engineering from Sri Venkateswara University in 2010, M.Tech in Embedded Systems from K.L.University in 2012. He holds a Doctoral Degree in Electronics and Communication Engineering from the National Institute of Technology Goa (2018) supported by Visvesvaraya Ph.D. Scheme, Government of India. He has also spent time with Intel Technology India Pvt. Ltd., Bangalore, as the Graduate Intern Technical. He has been with the Indian Institute of Technology Delhi as a Post-Doctoral Fellow (2020-2021). Presently he is an Assistant Professor at the Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu-620015, India

Dr. B. Naresh Kumar Reddy is currently involved in various teaching/research-related areas like Networks-on-Chip, Design methodologies for System-on-Chip, VLSI system design, FPGA implementation, Embedded Systems. He has published over 30 SCI Journals and 40 IEEE Conference papers and is a Senior Member of IEEE and a member of ACM. He has been recognized in the World's Top 2% of Most Influential Scientists for 2022, 2023, and 2024 by Stanford University. 

• FPGA Architectures  

• VLSI and Embedded Systems

• System-on-Chip/ Multiprocessor System-on-Chip/ Network-on-Chip

• Reconfigurable Architectures 

• System design using RISC-V based cores.

2025

[J32] (Elsevier) Aswin Sreekumar, Bolupadra Sai Shankar and B. Naresh Kumar Reddy, “Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability,” Integration, the VLSI Journal, Vol. 100, 2025. (Impact Factor= 2.5) https://doi.org/10.1016/j.vlsi.2024.102282 

[J31] (Taylor & Francis) Srinivasulu Jogi and B. Naresh Kumar Reddy, “Enhanced performance of full adder using advanced 9-T XOR-XNOR module,” International Journal of Electronics,1–20,2025. (ImpactFactor= 1.1) https://doi.org/10.1080/00207217.2025.2506020 

[J30] (Elsevier)  K.N. Vijeyakumar, Talluri Vineel Jessy, K. Saranya and B. Naresh Kumar Reddy, “Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures,” Integration, the VLSI Journal, Vol. 104, 2025. (Impact Factor = 2.5) https://doi.org/10.1016/j.vlsi.2025.102462 

[J29] (Springer) Ahmed, S., Ramesh, N.V.K. & B. Naresh Kumar Reddy, “An efficient routing mechanism for VANETs in SDN with hybrid meta-heuristic algorithm,” Telecommunication Systems, Vol. 88, 13, 2025. (Impact Factor= 1.7) https://doi.org/10.1007/s11235-024-01234-2 

[J28] (IET) Vydha Pradeep Kumar, Deepak Kumar Panda, Aruru Sai Kumar, B. Naresh Kumar Reddy, Ch. Rama Prakasha Reddy,“Analyzing Fully Depleted SOI NC-MOSFET for Enhanced Bio-Sensor and Digital Circuit Applications,” IET Circuits, Devices & Systems, Vol. 2025, Issue 1, Article ID: 5585625, 2025. (Impact Factor = 1.0). https://doi.org/10.1049/cds2/5585625.

[C17]  B Naresh Kumar Reddy, et al., “Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping,” 38th International Conference on VLSI Design & 24th International Conference on Embedded Systems (VLSID-2025), pp. 1-6, 2025. https://doi.org/10.1109/VLSID64188.2025.00019

 2024

[J27] (IEEE) B. Naresh Kumar Reddy, MZU Rahman, A Lay-Ekuakille, “Enhancing Reliability and Energy Efficiency in Many-Core Processors Through Fault-Tolerant Network-on-Chip,"  IEEE Transactions on Network and Service Management, Vol. 21, no. 5, pp. 5049-5062, 2024. (Impact Factor= 5.3). https://doi.org/10.1109/TNSM.2024.3394886

[J26]  (Elsevier) B. Naresh Kumar Reddy and A. Sai Kumar “Evaluating the Effectiveness of Bat Optimization in an Adaptive and Energy-Efficient Network-on-Chip Routing Framework,"  Journal of Parallel and Distributed Computing, 2024. (Impact Factor= 3.8). https://doi.org/10.1016/j.jpdc.2024.104853

[J25]  (Elsevier)  Batchu Veena Vani, Dharavath Kishan, Md Waseem Ahmad and B. Naresh Kumar Reddy, “An efficient battery swapping and charging mechanism for electric vehicles using bat algorithm,” Computers and Electrical Engineering, Volume 118, Part A, 2024. (Impact Factor= 4.3) https://doi.org/10.1016/j.compeleceng.2024.109357 

[C16]  B Naresh Kumar Reddy, et al., “Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization,” 37th International Conference on VLSI Design & 23rd International Conference on Embedded Systems (VLSID-2024), pp. 1-6, 2024. https://doi.org/10.1109/VLSID60093.2024.00118

[C15] B Naresh Kumar Reddy, et al., “Design and Implementation of an FPGA-based Emulator Circuit for MLP using Memristors,” 28th International Symposium on VLSI Design and Test (VDAT-2024), India, pp. 1-6, 2024.  https://doi.org/110.1109/VDAT63601.2024.10705433 

[C14] B Naresh Kumar Reddy, et al., “Design and Performance Evaluation of an Adaptive Routing Algorithm for RISC-V Based NoC Architecture,” 10th International Conference on Electronics, Computing and Communication Technologies, (CONECCT), IISc Bangalore, 2024.  https://doi.org/10.1109/CONECCT62155.2024.10677242

2023

[J24]  (Springer) A. Sai Kumar and B. Naresh Kumar Reddy, “An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip,” Wireless Personal Communications, Vol 128, pp.2937-2952, 2023. (Impact Factor= 2.2) https://doi.org/10.1007/s11277-022-10080-x 

[J23] (Springer) K. Sarangam, A. Sai Kumar and B. Naresh Kumar Reddy, “Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications,” Transactions on Electrical and Electronic Materials, 2023. (Impact Factor= 1.9) https://doi.org/10.1007/s42341-023-00503-2 

[J22] (Springer) Veena Vani, B., Kishan, D., Ahmad, M.W.and B. Naresh Kumar Reddy, “Bat Optimization Model for Electric Vehicle Route Optimization Under Time-of-Use Electricity Pricing,” Wireless Personal Communications, 2023. (Impact Factor= 2.2) https://doi.org/10.1007/s11277-023-10494-1

[J21] (Springer) M. Sree Chandana, K. Raghava Rao, B. Naresh Kumar Reddy. “Developing an adaptive active sleep energy efficient method in heterogeneous wireless sensor network,” Multimedia Tools and Applications, 2023. (Impact Factor= 3.6) https://doi.org/10.1007/s11042-023-16054-w

[J20]  (Springer) K. Raghava Rao, B. Naresh Kumar Reddy, and A. Sai Kumar “Using advanced distributed energy efficient clustering increasing the network lifetime in wireless sensor networks,”  Soft Computing, 2023. (Impact Factor= 4.1) https://doi.org/10.1007/s00500-023-07940-4

[J19] (Springer) Atiya, S.U., Ramesh, N.V.K. & B. Naresh Kumar Reddy “Classification of non-small cell lung cancers using deep convolutional neural networks,” Multimedia Tools and Applications, 2023. (Impact Factor= 3.6) https://doi.org/10.1007/s11042-023-16119-w

[C13] B Naresh Kumar Reddy, et al., “Enhancing the Accuracy and Resource Utilization of Field Programmable CRC Circuit Architecture,” 27th International Symposium on VLSI Design and Test (VDAT-2023), Bits Pilani, India, 2023.  https://doi.org/10.1007/978-981-97-3756-7_7

[C12] B Naresh Kumar Reddy, et al., “Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining,” 9th  IEEE International Symposium on Smart Electronic Systems (IEEE – iSES), 2023. https://doi.org/10.1109/iSES58672.2023.00090

[C11] B Naresh Kumar Reddy, Tharakeswar Appala and Veena “An Efficient Smart Gas Detecting System using MQ9 Sensor,” 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT), IIT Delhi, 2023. https://doi.org/10.1109/ICCCNT56998.2023.10307417

 2022

[J18] (Elsevier) B. Naresh Kumar Reddy, and Subrat Kar, “Performance evaluation of modified mesh-based NoC architecture,” Computers and Electrical Engineering, Volume 104, Part A, 2022. (Impact Factor= 4.3).  https://doi.org/10.1016/j.compeleceng.2022.108404

[J17]  (IEEE) K. Raghava Rao, Md Zia Ur Rahman, Krishna Prasad Satamraju and  B Naresh Kumar Reddy, “Genetic Algorithm for Cross-Layer based Energy Hole Minimization in Wireless Sensor Networks,” IEEE Sensors Letters, 2022. (Impact Factor= 2.8) https://doi.org/10.1109/LSENS.2022.3219857

[J16] (Springer) Pittala, C.S., Vijay, V. and B. Naresh Kumar Reddy, “1-Bit FinFET Carry Cells for Low Voltage High-Speed Digital Signal Processing Applications,” Silicon (2022). (Impact Factor= 3.4) https://doi.org/10.1007/s12633-022-02016-8

[J15] (Inderscience) A. Sai Kumar, TVK H Rao and B. Naresh Kumar Reddy, “Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures,” International Journal of Ad Hoc and Ubiquitous Computing, Vol 41, pp. 108-117, 2022. (Impact Factor= 0.773) https://doi.org/10.1504/IJAHUC.2022.125427

[J14]  (Springer) B. Naresh Kumar Reddy, B Seetharamulu, GS Krishna, BV Vani, “An FPGA and ASIC Implementation of Cubing Architecture,” Wireless Personal Communications, Vol. 125, pp. 3379-3391, 2022. (Impact Factor= 2.2). https://doi.org/10.1007/s11277-022-09715-w

[C10] B Naresh Kumar Reddy, Alex James and Sai Kumar, “Fault-tolerant Core Mapping for NoC Based Architectures with Improved Performance and Energy Efficiency,” 29th International Conference on Electronics, Circuits, and Systems (ICECS-2022), Glasgow, UK, Oct 24-26, 2022. https://doi.org/10.1109/ICECS202256217.2022.9970825

[C09]  B Naresh Kumar Reddy and A. Sai Kumar, “An Efficient Low-Power VIP-based VC Router Architecture for Mesh-based NoC,” IEEE 19th Indian Council International Conference (INDICON), Nov 24-26, 2022. https://doi.org/10.1109/INDICON56171.2022.10040017

2021

[J13] (Springer) Javvaji, V., Musala, S. and B. Naresh Kumar Reddy, “Continuous-time complex band-pass Gm-C sigma delta ADC with programmable bandwidths,” Analog Integrated Circuits and Signal Processing, Vol. 108, pp. 267–276, 2021. (Impact Factor= 1.4) https://doi.org/10.1007/s10470-021-01866-3

[C08] B Naresh Kumar Reddy and Subrat Kar “An Efficient Application Core Mapping Algorithm for Wireless Network-on-Chip,” 26th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2021), Dec 1– 4, in Perth, Australia, 2021. https://doi.org/10.1109/PRDC53464.2021.00028

[C07] B Naresh Kumar Reddy and Subrat Kar “Energy Efficient and High Performance Modified Mesh Based 2-D NoC Architecture,” 22nd IEEE International Conference on High Performance Switching and Routing (HPSR), June 7 – 9, in Paris, France, 2021. https://doi.org/10.1109/HPSR52026.2021.9481796

2020

[J12] (Springer) B. Naresh Kumar Reddy “Design and implementation of high performance and area efficient square architecture using Vedic Mathematics," Analog Integrated Circuits and Signal Processing, Vol. 102, pp. 501–506, 2020. (Impact Factor= 1.4) – Single Author https://doi.org/10.1007/s10470-019-01496-w

[J11]  (Springer) B. Naresh Kumar Reddy, BV Vani, GB Lahari “An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata," Telecommunication Systems, Vol. 74, pp. 487–496, 2020. (Impact Factor= 2.5) https://doi.org/10.1007/s11235-020-00669-7

[J10]  (Springer) Ahmed, S., Ramesh, N.V.K. and B. Naresh Kumar Reddy, “A Highly Secured QoS Aware Routing Algorithm for Software Defined Vehicle Ad-Hoc Networks Using Optimal Trust Management Scheme,” Wireless Personal Communications, Vol. 113, pp. 1807–1821, 2020. (Impact Factor= 2.2) https://doi.org/10.1007/s11277-020-07293-3

[C06]  B Naresh Kumar Reddy, G Sai Vishal Reddy, B Veena Vani, “Design and Implementation of an Efficient LFSR using 2-PASCL and Reversible Logic Gates,” IEEE Bombay Section Signature Conference (IBSSC), pp. 247-250, 2020. https://doi.org/10.1109/IBSSC51096.2020.9332213

 2019

[J09]  (Springer) B. Naresh Kumar Reddy, C Ramalingaswamy, R Nagulapalli, D Ramesh “A novel 8T SRAM with improved cell density,” Analog Integrated Circuits and Signal Processing, Vol. 98, Issue 2, pp. 357-366, 2019. (Impact Factor= 1.4) https://doi.org/10.1007/s10470-018-1309-z

[J08] (Springer) B. Naresh Kumar Reddy, Dharavath Kishan, and B. Veena Vani, “Performance constrained multi-application network on chip core mapping,” International Journal of Speech Technology, Vol 22, pp.927-936, 2019. https://doi.org/10.1007/s10772-019-09636-3

[C05]  B. Naresh Kumar Reddy, Sarangam K, T. Veeraiah and Ramalingaswamy Cheruku "SRAM cell with better read and write stability with Minimum area," IEEE TENCON 2019. https://doi.org/10.1109/TENCON.2019.8929593

 2018

[J07] (Elsevier) B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “An Energy Efficient Fault-Aware Core Mapping in Mesh-based Network on Chip Systems,” Journal of Network and Computer Applications, Vol. 105, pp. 79-87, 2018. (Impact Factor= 8.7) https://doi.org/10.1016/j.jnca.2017.12.019

[J06] (Springer) B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Hardware Implementation of Fault Tolerance NoC Core Mapping,” Telecommunication Systems (TELS), Vol 68, pp. 621- 630, 2018. (Impact Factor= 2.5)  https://doi.org/10.1007/s11235-017-0412-2

[J05] (Springer) B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Energy- Aware and Reliability- Aware Mapping for NoC-Based Architectures,” Wireless Personal Communications, Vol. 100, pp. 213- 225, 2018. (Impact Factor= 2.2) https://doi.org/10.1007/s11277-017-5061-y

[C04]  B. Naresh Kumar Reddy and Sireesha, “An Efficient Core Mapping Algorithm on Network on Chip,” 22nd International Symposium on VLSI Design and Test (VDAT), 2018. https://doi.org/10.1007/978-981-13-5950-7_52

 2017

[J04]  (Elsevier) B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “System Level Fault-Tolerance Core Mapping and FPGA-based Verification of NoC," Microelectronics Journal, Vol. 70, pp. 16- 26, 2018. (Impact Factor= 2.2) https://doi.org/10.1016/j.mejo.2017.09.010

[J03] (Elsevier) B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “High- Performance and Energy-Efficient Fault-Tolerance Core Mapping in NoC,” Sustainable Computing, Informatics and Systems, Vol. 16, pp. 1- 10, 2018. (Impact Factor= 4.5) https://doi.org/10.1016/j.suscom.2017.08.004

[J02]  (IET)  Ramalingaswamy Cheruku, Damodar Reddy Edla, Venkatanareshbabu Kuppili, Ramesh Dharavath, and B. Naresh Kumar Reddy, “Automatic Disease Diagnosis using Optimized Weightless Neural Networks for Low-Power Wearable Devices,” IET Healthcare Technology Letters, Vol.4, Iss.4, pp.122–128, 2017. (Impact Factor= 2.1) https://doi.org/10.1049/htl.2017.0003

[J01]  (Springer) Yehoshuva, C., B. Naresh Kumar Reddy., Ambati, V.R., “A novel CMOS Gmm-C complex filter design for multi-mode multi band wireless receiver applications,” Analog Integrated Circuits and Signal Processing, Vol. 91, pp. 43–51, 2017. (Impact Factor= 1.4) https://doi.org/10.1007/s10470-016-0823-0

2016

[C03]  B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare core,” 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), Pennsylvania, U.S.A., pp. 146-151, 2016. https://doi.org/10.1109/ISVLSI.2016.80

2015

[C02] B. Naresh Kumar Reddy, Vasantha.M.H., Nithin Kumar Y.B. and Dheeraj Sharma, “A Fine Grained Position for Modular Core on NoC,” IEEE International Conference on Computer, Communication and Control, Sep 2015. https://doi.org/10.1109/IC4.2015.7375574

[C01] B. Naresh Kumar Reddy, Vasantha.M.H., Nithin Kumar Y.B. and Dheeraj Sharma, “Communication Energy Constrained Spare Core on NoC,” 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Dallas, U.S.A., pp. 1-4, 2015. https://doi.org/10.1109/ICCCNT.2015.7395168

   Full Publications are available on Scopus

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