B. Naresh Kumar Reddy graduated B.Tech in Electronics and Communication Engineering from Sri Venkateswara University in 2010, M.Tech in Embedded Systems from K.L.University in 2012. He holds a Doctoral Degree in Electronics and Communication Engineering from the National Institute of Technology Goa (2018) supported by Visvesvaraya Ph.D. Scheme, Government of India. He has also spent time with Intel Technology India Pvt. Ltd., Bangalore, as the Graduate Intern Technical. He has been with the Indian Institute of Technology Delhi as a Post-Doctoral Fellow (2020-2021). Presently he is an Assistant Professor at the Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu-620015, India

Dr. B. Naresh Kumar Reddy is currently involved in various teaching/research-related areas like Networks-on-Chip, Design methodologies for System-on-Chip, VLSI system design, FPGA implementation, Embedded Systems. He has published over 30 SCI Journals and 40 IEEE Conference papers and is a Senior Member of IEEE and a member of ACM. He has been recognized in the World's Top 2% of Most Influential Scientists for 2022, 2023, and 2024 by Stanford University. 

• FPGA Architectures  

• VLSI and Embedded Systems

• System-on-Chip/ Multiprocessor System-on-Chip/ Network-on-Chip

• Reconfigurable Architectures 

• System design using RISC-V based cores.

2025

[C17]. B Naresh Kumar Reddy, et al., “Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping,” 38th International Conference on VLSI Design & 24th International Conference on Embedded Systems (VLSID-2025), 2025.  [https://doi.org/10.1109/VLSID64188.2025.00019]

2024

[J13]. B. Naresh Kumar Reddy, MZU Rahman, A Lay-Ekuakille, “Enhancing Reliability and Energy Efficiency in Many-Core Processors Through Fault-Tolerant Network-On-Chip,” IEEE Transactions on Network and Service Management, 2024. (Impact Factor= 5.3).  [https://doi.org/10.1109/TNSM.2024.3394886]

[J12]. B. Naresh Kumar Reddy and A. Sai Kumar “Evaluating the Effectiveness of Bat Optimization in an Adaptive and Energy-Efficient Network-on-Chip Routing Framework,"  Journal of Parallel and Distributed Computing, 2024.  (Impact Factor= 3.8). [https://doi.org/10.1016/j.jpdc.2024.104853]

[C16]. B Naresh Kumar Reddy, et al., “Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization,” 37th International Conference on VLSI Design & 23rd International Conference on Embedded Systems (VLSID-2024), 2024.  [https://doi.org/10.1109/VLSID60093.2024.00118]

[C15]. B Naresh Kumar Reddy, et al., “Design and Implementation of an FPGA-based Emulator Circuit for MLP using Memristors,” 28th International Symposium on VLSI Design and Test (VDAT-2024), India, 2024.  [https://doi.org/10.1109/VDAT63601.2024.10705433]

[C14]. B Naresh Kumar Reddy, et al., “Design and Performance Evaluation of an Adaptive Routing Algorithm for RISC-V Based NoC Architecture,” 10th International Conference on Electronics, Computing and Communication Technologies, (CONECCT), IISc Bangalore, 2024.  [https://doi.org/10.1109/CONECCT62155.2024.10677242] 

2023

[C13]. B Naresh Kumar Reddy, et al., “Enhancing the Accuracy and Resource Utilization of Field Programmable CRC Circuit Architecture,” 27th International Symposium on VLSI Design and Test (VDAT-2023), Bits Pilani, India, 2023.   [https://doi.org/10.1007/978-981-97-3756-7_7]

[C12]. B Naresh Kumar Reddy, et al., “Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining,” 9th  IEEE International Symposium on Smart Electronic Systems (IEEE – iSES), 2023.  [https://doi.org/10.1109/iSES58672.2023.00090]

[C11]. B Naresh Kumar Reddy, Tharakeswar Appala and Veena “An Efficient Smart Gas Detecting System using MQ9 Sensor,” 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT), IIT Delhi, 2023. [https://doi.org/10.1109/ICCCNT56998.2023.10307417]

2022

[J11]. B. Naresh Kumar Reddy and Subrat Kar “Performance evaluation of modified mesh-based NoC architecture," Computers and Electrical Engineering, Vol. 104, 2022.  (Impact Factor= 4.152). [https://doi.org/10.1016/j.compeleceng.2022.108404]

[C10]. B Naresh Kumar Reddy, Alex James and Sai Kumar, “Fault-tolerant Core Mapping for NoC Based Architectures with Improved Performance and Energy Efficiency,”  29th International Conference on Electronics, Circuits, and Systems (ICECS-2022), Glasgow, UK, Oct 24-26, 2022.

[https://doi.org/10.1109/ICECS202256217.2022.9970825]

[C9]. B Naresh Kumar Reddy and A. Sai Kumar, “An Efficient Low-Power VIP-based VC Router Architecture for Mesh-based NoC,” IEEE 19th Indian Council International Conference (INDICON), Nov 24-26, 2022.   [https://doi.org/10.1109/INDICON56171.2022.10040017]

[J10]. B. Naresh Kumar Reddy, B Seetharamulu, GS Krishna, BV Vani, “An FPGA and ASIC Implementation of Cubing Architecture,” Wireless Personal Communications, Vol. 125, pp. 3379-3391, 2022. (Impact Factor= 2.017)

[https://doi.org/10.1007/s11277-022-09715-w]

2021

[C8]. B Naresh Kumar Reddy and Subrat Kar “An Efficient Application Core Mapping Algorithm for Wireless Network-on-Chip,” 26th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2021), Dec 1– 4, in Perth, Australia, 2021.

[https://doi.org/10.1109/PRDC53464.2021.00028]

[C7]. B Naresh Kumar Reddy and Subrat Kar “Machine Learning Techniques for the Prediction of NoC Core Mapping Performance,” 26th  IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2021), Dec 1– 4, in Perth, Australia, 2021.

[https://doi.org/10.1109/PRDC53464.2021.00027]

[C6]. B Naresh Kumar Reddy and Subrat Kar “Energy Efficient and High-Performance Modified Mesh Based 2-D NoC Architecture,” 22nd IEEE International Conference on High Performance Switching and Routing (HPSR), June 7 – 9, in Paris, France, 2021.

[https://doi.org/10.1109/HPSR52026.2021.9481796]

2020

[J9]. B. Naresh Kumar Reddy “Design and implementation of high performance and area efficient square architecture using Vedic Mathematics," Analog Integrated Circuits and Signal Processing, Vol. 102, pp. 501–506, 2020. (Impact Factor= 1.321) -Single Author

[https://doi.org/10.1007/s10470-019-01496-w]

[J8]. B. Naresh Kumar Reddy, BV Vani, GB Lahari “An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata," Telecommunication Systems, Vol. 74, pp. 487–496, 2020. (Impact Factor= 2.336)

[https://doi.org/10.1007/s11235-020-00669-7]

[C5]. B Naresh Kumar Reddy, G Sai Vishal Reddy, B Veena Vani, “Design and Implementation of an Efficient LFSR using 2-PASCL and Reversible Logic Gates,” IEEE Bombay Section Signature Conference (IBSSC), pp. 247-250, 2020.

 [https://doi.org/10.1109/IBSSC51096.2020.9332213]

2019

[J7]. B. Naresh Kumar Reddy, Dharavath Kishan, and B. Veena Vani, “Performance constrained multi-application network on chip core mapping,” International Journal of Speech Technology, Vol 22, pp.927-936, 2019.

[https://doi.org/10.1007/s10772-019-09636-3]

[C4]. B. Naresh Kumar Reddy, Sarangam K, T. Veeraiah and Ramalingaswamy Cheruku "SRAM cell with better read and write stability with Minimum area," IEEE TENCON 2019

[https://doi.org/10.1109/TENCON.2019.8929593]

2018

[J6]. B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “An Energy Efficient Fault-Aware Core Mapping in Mesh-based Network on Chip Systems,” Journal of Network and Computer Applications, Vol. 105, pp. 79-87, 2018. (Impact Factor= 7.574)

[https://doi.org/10.1016/j.jnca.2017.12.019]

[J5]. B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Hardware Implementation of Fault Tolerance NoC Core Mapping,” Telecommunication Systems (TELS), Vol 68, pp. 621- 630, 2017. (Impact Factor= 2.336)

 [https://doi.org/10.1007/s11235-017-0412-2]

[C3]. B. Naresh Kumar Reddy and sireesha, “An Efficient Core Mapping Algorithm on Network on Chip,” 22nd International Symposium on VLSI Design and Test (VDAT), 2018.

[https://doi.org/10.1007/978-981-13-5950-7_52]

[J4]. B. Naresh Kumar Reddy, C Ramalingaswamy, R Nagulapalli, D Ramesh, “A novel 8T SRAM with improved cell density,” Analog Integrated Circuits and Signal Processing, Vol. 98, Issue 2, pp. 357-366, 2018. (Impact Factor= 1.321)

[https://doi.org/10.1007/s10470-018-1309-z]

[J3]. B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Energy Aware and Reliability- Aware Mapping for NoC-Based Architectures,” Wireless Personal Communications, Vol. 100, pp. 213- 225, 2017. (Impact Factor= 2.017)

[https://doi.org/10.1007/s11277-017-5061-y]

2017

[J2]. B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “System Level Fault-Tolerance Core Mapping and FPGA-based Verification of NoC," Microelectronics Journal, Vol. 70, pp. 16- 26, 2017. (Impact Factor= 1.992)

 [https://doi.org/10.1016/j.mejo.2017.09.010]

[J1]. B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “High- Performance and Energy-Efficient Fault-Tolerance Core Mapping in NoC,” Sustainable Computing, Informatics and Systems, Vol. 16, pp. 1- 10, 2017. (Impact Factor= 4.923)

 [https://doi.org/10.1016/j.suscom.2017.08.004]

2016

[C2]. B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare core,” 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), Pennsylvania, U.S.A., pp. 146-151, 2016

[https://doi.org/10.1109/ISVLSI.2016.80]

2015

[C1] B. Naresh Kumar Reddy, Vasantha.M.H., Nithin Kumar Y.B. and Dheeraj Sharma, “Communication Energy Constrained Spare Core on NoC,” 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Dallas, U.S.A., pp. 1-4, 2015.

[https://doi.org/10.1109/ICCCNT.2015.7395168]

   Full Publications are available on Scopus

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