Many times I needed to have a look at analog and digital waveforms in the device after a specific event in it happened. Such events can be a software subroutine call, a transaction on a SPI or I2C interface, or some sequence of digital signals on a bus. I used Tektronix logic analyzers which are good at capturing logic events comprised from multiple digital lines. But they are large, and inherently cannot interpret serial communication protocols and trigger on a specific data transaction. I also used few MSOs, they are handy but their digital capture section is not flexible today to detect and trigger on specific transaction. Unlike LA, entry level MSOs lack ability to operate on different popular LVCMOS logic levels. Besides many logical probe leads connected directly to scope front panel make testbench too congested.

I gradually switched to a logic capture and trigger pre-processor build on a generic low cost FPGA, which I configure for a specific measurements by implementing protocol converters and trigger logic and state machines. The configuration is developed as a Verilog RTL and compiled into FPGA with vendor's free development tools. The density of such FPGA does not need to be huge, the lower end members of Xilinx Spartan or Artix family are quite sufficient.

These FPGAs have multiple I/O banks, and each bank can act as a level translation front end, accepting LVCMOS at different levels, as well as various differential signals. The inputs may also enable termination resistors when needed. The FPGA-based front end can handle all my mid-range logic analysis needs, with the sample rates at 250/500MHz. It may be placed side-by side with a device under test, and the wiring will be short and low-capacitance.

The only remaining problem is how to run the output signals to the scope over few feet without a wire mess on the bench.

The idea is pretty obvious but it brings many benefits to the scope if implemented in commercial instrument.

First, the scope can have several pre-configured bitstreams for typical measurements and standard protocols, and user may load these configurations to SmartPod from internal scope storage.

Second, the user may develop their own configurations, and upload it to scope's memory or probe through standard PC communication method and VISA protocol. Each test application is different, but open architecture of the SmartPod will make such instruments much more appealing. The vendor may also offer additional application packages for SmartPod.

Finally, the user may enhance capture and triggering capability by changing the combination of data width and sample rate, and implement state machines when needed. Additional memory to add decent MSO capability to entry level scope is equivalent to one-two extra analog channels, and is not expensive with todays' DRAM devices.

Probably, a tool for assembling configuration from standard building blocks in a graphical user interface will make this task even more intuitive and easy.

I am wondering why the entry level digital scope vendors are not implementing and selling such adder - it could make their instruments much more appealing and handy for the average engineer.