Google Scholar ~ https://scholar.google.co.in/citations?user=HIlJrG0AAAAJ&hl=en
Linked in ~ https://in.linkedin.com/in/dipankarsaha2013dese
ResearchGate ~ https://www.researchgate.net/profile/Dipankar-Saha-14
Primary Email Id: dipsah_etc@yahoo.co.in
Dipankar Saha is currently working with the Department of Electronics and Communication Engineering, NiT Agarpara, Kolkata as an Associate Professor (05/09/2024 - Present). Dipankar Saha worked with the Institute of Engineering and Management (IEM) Kolkata as an Associate Professor (03/10/2023 - 28/06/2024). Dipankar Saha previously worked with the Department of Electronics and Telecommunication Engineering, IIEST Shibpur as a Faculty from 27/10/2020 to 31/08/2023. Besides, he worked with the Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT B) as a “Post Doctoral Fellow” (03/2018 to 10/2020). He obtained his PhD from the Indian Institute of Science (IISc), Bangalore in 2017. His current research interests include modeling and simulation of nano-scaled devices with 2D channel materials, beyond CMOS technology and devices, 2D material-based vdW heterostructures, and electro-thermal transport in nanoelectronic devices. Dipankar Saha is a senior member of IEEE Electron Devices Society (M’17 & SM’22). Besides, he is the reviewer of several international journals e.g. ACS Applied Materials & Interfaces, IEEE Transactions on Electron Devices, Nanoscale Research Letters Springer, Scientific Reports Nature, Applied Surface Science Elsevier, 2D Materials IOP Publishing, etc.
Research Interests
Modeling and Simulation of Nano-scaled Devices with 2D channel materials/
Ultra-low power digital/analog-mixed signal circuits and system design /
Beyond CMOS Technology and Devices /
Electro-thermal transport properties of Nano-electronic Devices /
2D material-based vdW Heterostructures /
Study of Interfaces and Defects in 2D materials
Teaching
Courses
PECEC Nano Electronics (Under Graduate)
ET 5108 Analog VLSI Design (Post Graduate)
ET5224 RF IC (Post Graduate)
ET 5210 Low Power VLSI Design (Post Graduate)
ET 3202 VLSI and CAD (Under Graduate)
ET 721/1 Audio and Video Systems (Under Graduate)
ET 3205 Computer Organization and Architecture (Under Graduate)
Labs / Sessional Subjects
OEC481 Object Oriented Programming (Under Graduate)
ET 5178 VLSI Design Lab. (Post Graduate)
ET 2174 Modeling and Simulation Lab. (Under Graduate)
ET 4172 VLSI and CAD Lab. (Under Graduate)
Selected Publications
Journal Publications
1) Dipankar Saha and Saurabh Lodha, “First-principles based simulations of electronic transmission in ReS2/WSe2 and ReS2/MoSe2 type-II vdW heterointerfaces,” Scientific Reports, 11, 23455, 2021
2) Dipankar Saha, Abin Varghese, and Saurabh Lodha, “Atomistic Modeling of van der Waals Heterostructures with Group-6 and Group-7 Monolayer Transition Metal Dichalcogenides for Near Infrared/Short-wave Infrared Photodetection,” ACS Appl. Nano Mater., 3, 1, 820-829, 2020
3) Abin Varghese, Dipankar Saha, Kartikey Thakar, Vishwas Jindal, Sayantan Ghosh, Nikhil V Medhekar, Sandip Ghosh and Saurabh Lodha, “Near-Direct Bandgap WSe2/ReS2 Type-II pn Heterojunction for Enhanced Ultrafast Photodetection and High-Performance Photovoltaics,” Nano Lett., 20, 3, 1707- 1717, 2020
4) Dipankar Saha and Santanu Mahapatra, “Anisotropic transport in 1T’ monolayer MoS2 and its metal interfaces,” Physical Chemistry Chemical Physics, Royal Society of Chemistry, 19, 10453-10461, 2017
5) Dipankar Saha and Santanu Mahapatra, “Asymmetric Junctions in Metallic-Semiconducting-Metallic Heterophase MoS2 ,” IEEE Transactions On Electron Devices, vol. 64, no. 5, 2457-2460, 2017
6) Dipankar Saha and Santanu Mahapatra, “Atomistic modeling of the metallic-to-semiconducting phase boundaries in monolayer MoS2,” Applied Physics Letters, AIP Publishing, 108, 253106, 2016
7) Dipankar Saha and Santanu Mahapatra, “Theoretical insights on the electro-thermal transport properties of monolayer MoS2 with line defects,” Journal of Applied Physics, AIP Publishing, 119, 134304, 2016
8) Dipankar Saha and Santanu Mahapatra, “Analytical insight into the lattice thermal conductivity and heat capacity of monolayer MoS2,” Physica E: Low-Dimensional Systems and Nanostructures, Elsevier, 83, 455-460, 2016
9) Arup Kumar Paul, Manabendra Kuiri, Dipankar Saha, Biswanath Chakraborty, Santanu Mahapatra, A.K. Sood, and Anindya Das, “Photo-tunable transfer characteristics in MoTe2-MoS2 vertical heterostructure,” npj 2D Materials and Applications, Nature Partner Journals, 17, 2017
10) Madhuchhanda Brahma, Arnab Kabiraj, Dipankar Saha, and Santanu Mahapatra, “Scalability assessment of Group-IV monochalcogenide based tunnel FET,” Scientific Reports, Nature, 8:5993, 2018
11) Sitangshu Bhattacharya, Dipankar Saha, Aveek Bid and Santanu Mahapatra, “A Continuous Electrical Conductivity Model For Monolayer Graphene From Near Intrinsic to Far Extrinsic Region,” IEEE Transactions on Electron Devices, vol. 61, no. 11, 2014
12) Dipankar Saha, Aanan Chatterjee, Sayan Chatterjee, and C. K. Sarkar, “Row-Based Dual Vdd Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation,” Advances in Electrical Engineering, Hindawi Publishing Corporation, article ID 814975, 6 pages, 2014
Conference Proceedings
i) Arun KP, Jehan Taraporewalla, and Dipankar Saha: Transistor Size Optimized Ultra-low Power NNPT and PNPT Level Converter Designs. 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech); 12/2023
ii) Jehan Taraporewalla and Dipankar Saha: A New 22 nm ULPLS Architecture to Detect 70 mV Minimum Input, Suitable for IOT Applications. 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech); 12/2023
iii) Sarvam Kesharwani, Jehan Taraporewalla, and Dipankar Saha: Single Threshold TSO Level Converters for Ultra-Low Power Digital Designs. 19th INDICON; 2022
iv) Yuvam Bhateja, Joshua Roy Palathinkal, Tamajeet Mandal, Pronay Roy, and Dipankar Saha: Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2. 25th International Symposium on VLSI Design and Test (VDAT); 09/2021
v) Dipankar Saha and Saurabh Lodha: Study of Transmission Properties of Distorted 1T ReS2 Based Type-II van der Waals Heterostructures. Materials Research Society 2020 MRS Fall Meeting; 11/2020 – 12/2020
vi) Richa Chakravarty, Dipankar Saha and Santanu Mahapatra: New Asymmetric Atomistic Model for the Analysis of Phase-engineered MoS2-Gold Top Contact. IEEE 31st International Conference on VLSI Design (VLSID); 01/2018
vii) Dipankar Saha, Sitangshu Bhattacharya and Santanu Mahapatra: Modeling of Sheet-concentration and Temperature-dependent Resistivity of a Suspended Monolayer Graphene. IEEE 2nd International Conference on Emerging Electronics (ICEE); 12/2014
viii) Dipankar Saha, Subhramita Basak, Sagar Mukherjee and C. K. Sarkar: A low-voltage, Low-Power 4-bit BCD adder, designed using the Clock Gated Power Gating, and the DVT scheme. IEEE International Conference on Signal Processing, Computing and Control (ISPCC); 09/2013
ix) Sagar Mukherjee, Dipankar Saha, Posiba Mostafa, Sayan Chatterjee and C. K. Sarkar: A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications. IEEE International Symposium on Electronic System Design (ISED); 12/2012
x) Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee and C. K. Sarkar: Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, modified with the concept of MVT Scheme. IEEE International Symposium on Electronic System Design (ISED); 12/2012