Just Accepted Articles

International Conference Article

[13]   Jugal Gandhi, Diksha Shekhawat, M. Santosh, and Jai Gopal Pandey. “Emerging Frontiers and Limitations of Logic Locking for Secure IC Design,” 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Kuala Lumpur, Malaysia. [Accepted for Oral Presentation]

Published Articles

Peer Reviewed Journal Articles

[12]  Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey, “GAN4IP: A Unified GAN & Logic Locking-based Pipeline for Hardware IP Security,” Sādhanā- Academy Proceedings in Engineering Sciences, doi: https://doi.org/10.1007/s12046-024-02461-8. [SCI, Q2, Impact Factor: 1.6]

[11]  Kartik Jhawar, Jugal Gandhi, Diksha Shekhawat, Aniket Upadhyay, Avadh Harkishanka, Nitin Chaturvedi, M Santosh, Jai Gopal Pandey, “Modeling, Hardware Architecture, and Performance Analyses of an AEAD-based Lightweight Cipher,” Real-time Image Processing. doi: https://doi.org/10.1007/s11554-024-01416-w  [SCI, Q2, Impact Factor: 3.0, Citation: 02]

[10] Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey, “Logic Locking for IP Security: A Comprehensive Analysis on Challenges, Techniques, and Trends,” Computers & Security, Volume 129, 2023, 103196, ISSN 0167-4048, doi: https://doi.org/10.1016/j.cose.2023.103196 [SCI, Q1, Impact Factor: 5.6, Citation: 09] 

[9] Rudresh Pratap Singh, Shreyam Kumar, Jugal Gandhi, Diksha Shekhawat, M Santosh, Jai Gopal Pandey, “A Time Domain 2D OaA-based Convolutional Neural Networks Accelerator,” Memories-Materials, Devices, Circuits and Systems, Volume 4, 2023, 100041. doi: https://doi.org/10.1016/j.memori.2023.100041 [Non-SCI, Publisher: Elsevier, Citation: 03]

Flagship Ranked Conference Articles

[8]  Jugal Gandhi, Diksha Shekhawat, M. Santosh, and Jai Gopal Pandey. “SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking,” 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, pp. 547-552, doi: https://doi.org/10.1109/VLSID60093.2024.00097. [Citation: 00] 

[7]  Jugal Gandhi, Diksha Shekhawat, M. Santosh, and Jai Gopal Pandey. “Security Evaluation of Lightweight SBoxes,” 2023 IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, India, pp. 315-318, doi: https://doi.org/10.1109/iSES58672.2023.00071. [Citation: 00]  

[6]  Jugal Gandhi, Diksha Shekhawat, M. Santosh, and Jai Gopal Pandey. “LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking,” 202319th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Hyderabad, India, pp 85-89. doi: https://doi.org/10.1109/APCCAS60141.2023.00030  [Citation: 01]  

[5]  Diksha Shekhawat, Jugal Gandhi, Ranjeeth Sekhar CB, M. Santosh, and Jai Gopal Pandey. “A NAND Flash Memory Controller for Energy-Constrained Edge Computing Applications,” 2023 27th International Symposium on VLSI Design and Test (VDAT), Pilani, India, doi:. [Citation: 00] 

[4]  Jugal Gandhi, Diksha Shekhawat, M. Santosh, and Jai Gopal Pandey. “LightLock: Lightweight Logic Locking for Hardware IP Security,” 2023 27th International Symposium on VLSI Design and Test (VDAT), Pilani, India, doi: . [Citation: 00] 

[3]  Diksha Shekhawat, Jugal Gandhi, M Santosh, Jai Gopal Pandey, “PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations,” 2023 4th International Conference on Next Generation Arithmetic, Singapore. doi: https://doi.org/10.1007/978-3-031-32180-1_6 [Citation: 00] 

[2]  Apoorva Jangir, Diksha Shekhawat and Jai Gopal Pandey, “An FPGA Prototyping of the GIFT Cipher for Image Security Applications,” 2021 4th International Conference on Security and Privacy (ISEA-ISAP), Dhanbad, India. doi: https://doi.org/10.1109/ISEA-ISAP54304.2021.9689764 [Citation: 00] 

[1]   Diksha Shekhawat, Apoorva Jangir and Jai Gopal Pandey, “A Hardware Generator for Posit Arithmetic and its FPGA Prototyping,” 2021 25th International Symposium on VLSI Design and Test (VDAT), Surat, India. doi: https://doi.org/10.1109/VDAT53777.2021.9601025 [Citation: 04] 

Under Review *

Diksha Shekhawat, Jugal Gandhi. M. Santosh, Jai Gopal Pandey, Chandra Shekhar 

MLOD: Resource Efficient Posit Data Decoder

IEEE Transactions  [SCI, Q1]

Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey, 

Logic Obfuscated Crypto-accelerator for Secure Image Communication 

IEEE Transactions  [SCI, Q1]

Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey, 

Decoding Nibbles: A Security Evaluation of Lightweight 4-bit S-boxes 

WPCJ. [SCI, Q2]

Ranjeeth Sekhar CB, Diksha Shekhawat, Jugal Gandhi, M. Santosh, and Jai Gopal Pandey, 

Energy and Performance Efficient NAND Flash Translation Layer Architecture for Low-latency Edge Applications 

JPDC. [SCI, Q1]

*follows a single-blind review 

Other International Conference Articles Under Review: 03 A-Ranked Conference 

Google Scholar Profile