Diksha Shekhawat

Ph.D. Scholar | M.Tech. (Advanced Electronics Engineering) | B.Tech. (Electronics and Communication Engineering)

I am a Ph.D scholar and Project Associate-I at CSIR-CEERI (Government of India), Pilani, under the Academy of Scientific and Innovative Research (AcSIR). I did an M.Tech. in Advanced Electronics Engineering from CSIR-CEERI (Government of India), Pilani, under AcSIR, and a B.Tech. in Electronics and Communication Engineering (ECE) from BKBIET, Pilani.

My research interests include computer architectures, computer arithmetic, posit accelerators, digital logic design, VLSI design, RTL design, SoC, hardware security, secure processor design, FPGAs, etc.

Quote of the day:

"Pure mathematics is, in its way, the poetry of logical ideas."

- Albert Einstein

ACADEMIC BACKGROUND

PhD (Engineering Sciences) Scholar [Jan. 2022 - Present]

Academy of Scientific and Innovative Research (AcSIR) [NIRF Ranking: 12 (Research Category)]
Council of Scientific & Industrial Research (CSIR) - Central Electronics Engineering Research Institute (CEERI) (Government of India), Pilani
Proposed Research Direction: Posite Arithmetic ALU Accelerator for Edge Computing
Supervisor: Dr. Jai Gopal Pandey, Principal Scientist, CSIR-CEERI [Link]
Co-supervisor: Dr. Chandra Shekhar, Senior Professor Emeritus, BITS Pilani [Ex-Chancellor, AcSIR and Ex-Director, CSIR-CEERI] [Link]

M.Tech. (Advanced Electronics Engineering) [Aug. 2019 - Aug. 2021]

Academy of Scientific and Innovative Research (AcSIR)
CSIR-CEERI (Government of India), Pilani
Supervisor: Dr. Jai Gopal Pandey, Principal Scientist, CSIR-CEERI [Link]
Thesis Title: An Efficient Architecture for Posit Arithmetic and its FPGA Implementations
- Hardware modeling of Posit adder/subtractor and multiplier has been done using VHDL
- Synthesized and implemented on Xilinx Vivado tool, then analyzed on the FPGA boards
Minor Project:
- Encryption and decryption of data have been done using simplified DES and DES cipher
- Plaintext of 64-bit is converted into ciphertext using the 48-bit key

B.Tech. (Electronics and Communication Engineering) [Aug. 2015 - Aug. 2019]

B.K. Birla Institute of Engineering & Technology (BKBIET), Pilani

WORK EXPERIENCE

Designation: Project Associate-I

Duration: Mar. 2024 - Present
Place: CSIR-CEERI (Gov. of India), Pilani, India
Project Title: Hardware IP Protection for Secure IC Design using Intelligent Logic Locking
Funded by: Science and Engineering Research Board (SERB) - Department of Science and Technology (DST) - Core Research Grant
- Hardware modeling of secure IP design scheme using pre-synthesis logic locking technique
- Functional obfuscated reverse engineering secure cryptographic IP/IC design and its ASIC prototyping on TSMC 28nm CMOS technology node

Designation: Project Associate-I

Duration: Nov. 2022 - Nov. 2022
Place: CSIR-CEERI (Gov. of India), Pilani, India
Project Title: Hardware Architecture and Design of a NAND Flash Memory Data Controller
Funded by: CSIR-CEERI (Gov. of India), Pilani, India
- Hardware modeling of memory interface controller for Samsung NAND flash memory using VHDL
- Functional simulations of building blocks have been done in the Modelsim simulator. Synthesized and implemented on Xilinx Vivado tool, then analyzed on FPGA

RESEARCH INTEREST

TECHNICAL SKILLS

Hardware | Software Languages: VHDL, Verilog | C, C++, Python

EDA Tools: Xilinx Vivado, Xilinx ISE, ModelSim, Synopsys Design Compiler, Synopsys IC Compiler, Multisim, MATLAB

CMOS Technology Node: TSMC 28nm, UMC 22/28/40/65/180nm, SCL 180nm

FPGA Prototyping Boards: Zynq Ultrascale+, Virtex-7, Virtex-5, Zybo, etc.

Evaluation Boards: Arduino

Misc.: Academic Research, Teaching, Training, LaTeX Typesetting and Publishing

Operating Systems: Linux, Windows

Recent Research Work:

A physical design layout has been developed for the Posit Multiplier Accelerator using Synopsys IC Compiler II on a 32nm CMOS technology node. The design takes a total cell area of 7323 um^2 with a core utilization of 70.3%.

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