Teaching
CSE 140 - Digital System Design
When I was a Teaching Assistant for Digital System Design (CSE140) at UC San Diego, I made videos in my free time to help my students understand the concepts better. For each video, I spent at least 8 hours trying to come up with the best way to explain the materials. Sometimes, it took me more than a week to figure it out. These hours were unpaid, but I received a lot of love and support from my students that I continued making more videos. I still keep the videos up and it makes me smile whenever I get a random "thank you" message from new students :)
Youtube channel: https://www.youtube.com/c/cs3girl
Student evaluations:
StudentEvals.pdfStudent Evals2.pdfMIDTERM 1
Sometimes it's tricky to find the best number to pick when you build a graph. My suggestion was to pick a number that HASN'T appeared yet. But what if sometimes there is a number that has appeared in one branch, but not in the others? Here is an example:
So our list is 2,3,4,7. Now if I pick 3, I have m(2,3) and m(3,7). Next I pick 4 since 4 hasn't appeared yet. This is what happens next:
For POS, you do the exact same thing but circle the 0's instead, and write f in terms of M and pick numbers from that list.
MIDTERM 2
Videos:
3. Implement JK Flip Flop using T Flip Flop
I covered how to get the state table and excitation table in the videos.
In short:
- For these kinds of latches/flip flops, we already know how they behave, so we can get the state table easily (like what i did in the video). From state table, we can get the excitation table.
- If we don't know how they work, the problem usually gives us some equations like this:
Q1(t+1)=Q0(t)+Q′1(t)x(t)
Q0(t+1)=Q1(t)+Q0(t)x(t)
y(t)=Q1(t)Q0(t)+x(t)
From those equations, we can get the state table: given Q_1(t), Q_0(t), input x(t), what is Q_1(t+1), Q_0(t+1), output y(t)? Just plug the values into the above equations. From the state table, we can get the excitation table.
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I didn't cover how to draw timing diagrams for SR & JK, but if you already have the state table, it's very simple.
For SR: whenever either S or R changes, look at the values of SR & the state table to figure out what Q is.
For JK: whenever the clock changes from 0 to 1, look at the values of JK & the state table to figure out what Q is.
Make sure you know how to draw timing diagrams!
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FAQs:
1. Do D-latch and D-flip flop have the same state table and excitation table?
Yes, they do! When we write the state table and excitation table, we usually leave out the "CLK". D latch and D flipflop behave the same way except for the CLK part. We look at the whole interval when CLK = 1 for D latch, but only look at the rising edge (when CLK changes from 0 to 1) for D flip flop.
2. Dao showed 2 ways of drawing state tables. One had the present state along the left hand side, the inputs along the top, and the next state on the inside of the table. Another way looked more like a truth table with the present state, next state, and inputs along the top. Are both ways acceptable on the midterm ?
Both ways are correct. What I suggest is:
For JK, SR, D, T, use the first way (like in the summary sheet I give)
For other cases (when they give you a set of equations), use the 2nd way. Why? Because there are so many variables, the solution's way looks cleaner.
3. What's the difference between a truth table and state table? The solution on the video looks to be a truth table so I'm a bit confused
To be precise, the solution's state table in the slides has more information than a state table requires. They combine step 1,2,3 together. I just broke down the steps so it's easier for you guys to see/understand.
The truth table combines the state table & excitation table together. If they ask for state table, you can stop at step 1, but include output y as well.
latchffsummary_sheet1.pdfMIDTERM 3
Videos:
1. Multiplexer Part 1 Multiplexer Part 2 (I forgot the inside labels for the selectors. Please remember to label them)
2. Data Subsystem Reg B and Reg C should be named Counter B and Counter C to be precise (since we have INC in it).
Notes:
FAQs:
1. Different orders of selectors give me different designs. Do I need to try all the possible combinations to get the minimal network?
No. We don't care about the ordering of the selectors. However, for the ordering that you choose, the circuit has to be minimal. So make sure your Kmap and everything else are correct.
2. For one-hot state machine, can I use a demux instead of AND gates?
Both ways are fine.
3. For the output in the data subsystem, how do I know when to use wires and when to use a register?
Both solutions are acceptable.
4. When do I name it Register A? When do I name it Counter A?
The function of the register is a subset of the function of a counter.
When you have just LD or CLR, you can name it Register A. When you also have INC, you can name it Counter A.
5. Does it matter how I name my control signals? For example, my C3 is your C0. Is that okay?
Yes, that's fine. But make sure your table corresponds to your design.
6. Is there a list of operations (like decrementing and subtracting) for planning out the data subsystem?
You can assume we have modules for the following operations: INC, DEC, SUB, ADD, COMP, SHL, SHR, LD, CLR, CS (change sign) etc.
7. So in the video, you have "Inc" on the register, but "Add" is a separate block, when are we allowed to put it on the register, and when do we need it to be on a separate block?
They can all be in separate blocks.
We combine DEC, INC, LD, CLR in one single block is because these operations are simple. ADD takes 2 inputs so we would need to get the inputs from somewhere. It's also a rather complicated operation so we have a separate module for it.
A general guideline is:
- SUB, ADD, COMP, SHL, SHR are separate boxes.
- DEC, INC, LD, CLR, CS can be in one box.
