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A photo with the mascot bear at UCLA.
A photo with the mascot bear at UCLA.
Danyoung Cha (차단영), Ph.D
Danyoung Cha (차단영), Ph.D
Research Professor, Semiconductor-Specialized University, Pusan National University (부산대학교 반도체특성화대학 사업단)
Research Professor, Semiconductor-Specialized University, Pusan National University (부산대학교 반도체특성화대학 사업단)
Address: 408, Engineering Building. #8, 2, Busandaehag-ro, 63Beon-gil, Geumjeong-gu, Busan 46241, Republic of Korea.
E-mail: wdwn9277@pusan.ac.kr
E-mail: wdwn9277@pusan.ac.kr
Education
Education
Ph.D. Department of Electrical and Electronics Engineering, Pusan National University (2019.3 - 2025.2)
Ph.D. Department of Electrical and Electronics Engineering, Pusan National University (2019.3 - 2025.2)
(Thesis Title: A Technology Development of Low-Power Synaptic Devices Based on Amorphous Oxide Semiconductors) (Advisor: Prof. Sungsik Lee)
B.S. (Summa Cum Laude) Department of Electronics Engineering, Pusan National University (2015.3 - 2019.2)
B.S. (Summa Cum Laude) Department of Electronics Engineering, Pusan National University (2015.3 - 2019.2)
Professional Experiences
Professional Experiences
Research Professor at Pusan National University (2025.4 - Present)
Research Professor at Pusan National University (2025.4 - Present)
Research Interest
Research Interest
Ultra-low Power Synaptic Devices (Synaptic Transistors)
Ultra-low Power Synaptic Devices (Synaptic Transistors)
A neuromorphic system, which mimics behaviors of a biological nervous system, has been considered as a promising candidate due to a more efficient computing capability compared to the conventional computer system based on the von Neumann architecture. Besides a higher data processing efficiency of the neuromorphic system, a low-power characteristics of a synaptic device, which is a fundamental building block, is essential for a high-level intelligence of the system. Here, it is known that a level of the intelligence is proportional to the number of synaptic devices, resulting in the increase of a total power consumption proportionally. In this respect, the power consumption of a single synaptic device has to be minimized. For reducing the power consumption of the device, the synaptic TFT (Syn-TFT) can be operated in a sub-threshold region due to a lower current level compared to an above-threshold region. In addition, for ultra-low power consumption, a synaptic pass-transistor (SPT) can be employed where the Syn-TFT is connected in series with a load TFT. Research papers associated with these devices are here.
A neuromorphic system, which mimics behaviors of a biological nervous system, has been considered as a promising candidate due to a more efficient computing capability compared to the conventional computer system based on the von Neumann architecture. Besides a higher data processing efficiency of the neuromorphic system, a low-power characteristics of a synaptic device, which is a fundamental building block, is essential for a high-level intelligence of the system. Here, it is known that a level of the intelligence is proportional to the number of synaptic devices, resulting in the increase of a total power consumption proportionally. In this respect, the power consumption of a single synaptic device has to be minimized. For reducing the power consumption of the device, the synaptic TFT (Syn-TFT) can be operated in a sub-threshold region due to a lower current level compared to an above-threshold region. In addition, for ultra-low power consumption, a synaptic pass-transistor (SPT) can be employed where the Syn-TFT is connected in series with a load TFT. Research papers associated with these devices are here.
News
News
2025.09.08. My research paper (Corresponding Author) related to Syn-TFTs has been accepted to IEEE T-ED (Link).
2025.09.08. My research paper (Corresponding Author) related to Syn-TFTs has been accepted to IEEE T-ED (Link).
2025.08.30. My conference paper (First Author) related to SPTs has been accepted to 56th IEEE SISC 2025.
2025.08.30. My conference paper (First Author) related to SPTs has been accepted to 56th IEEE SISC 2025.
2025.06.18. My research paper (Corresponding Author) related to Syn-TFTs has been accepted to IEEE T-ED (Link).
2025.06.18. My research paper (Corresponding Author) related to Syn-TFTs has been accepted to IEEE T-ED (Link).
2025.05.15. My research paper (First Author) related to SPTs has been accepted to ACS Applied Materials & Interfaces (Link).
2025.05.15. My research paper (First Author) related to SPTs has been accepted to ACS Applied Materials & Interfaces (Link).
2025.03.26. My research paper (First Author) related to Syn-TFTs has been accepted to Scientific Reports (Link).
2025.03.26. My research paper (First Author) related to Syn-TFTs has been accepted to Scientific Reports (Link).
2024.12.20. My research paper (First Author) related to Syn-TFTs has been accepted to ACS Applied Electronic Materials (Link).
2024.12.20. My research paper (First Author) related to Syn-TFTs has been accepted to ACS Applied Electronic Materials (Link).
2024.11.20. My research paper (First Author) related to Hf-ZnO TFTs has been accepted to IEEE ACCESS (Link).
2024.11.20. My research paper (First Author) related to Hf-ZnO TFTs has been accepted to IEEE ACCESS (Link).
2024.11.09. My research paper (First Author) related to Synaptic Hf-ZnO TFTs has been accepted to IEEE ACCESS (Link).
2024.11.09. My research paper (First Author) related to Synaptic Hf-ZnO TFTs has been accepted to IEEE ACCESS (Link).
2024.09.03. My conference paper (First Author) related to SPTs has been accepted to 55th IEEE SISC 2024.
2024.09.03. My conference paper (First Author) related to SPTs has been accepted to 55th IEEE SISC 2024.
2024.04.24. My research paper (First Author) related to SPTs has been accepted to Advanced Electronic Materials (Link).
2024.04.24. My research paper (First Author) related to SPTs has been accepted to Advanced Electronic Materials (Link).
2022.12.09. My research paper (First Author) related to Synaptic IGZO TFTs has been accepted to Scientific Reports (Link).
2022.12.09. My research paper (First Author) related to Synaptic IGZO TFTs has been accepted to Scientific Reports (Link).
2022.03.25. My research paper (First Author) related to a low power SPT has been accepted to IEEE ACCESS (Link).
2022.03.25. My research paper (First Author) related to a low power SPT has been accepted to IEEE ACCESS (Link).
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