Speakers

Programming Heterogeneous Devices with MLIR

Abstract

With the slowing of longtime trends in CMOS technology scaling, many people are looking towards a ‘new golden age of computer architecture’ to enable new differentiated devices. Many of these new computer architectures require rethinking the way that programmers think about their applications, requiring new tools and compilers to unlock the power of these devices. This talk will focus on our work using multiple levels of abstraction, expressed in the MLIR compiler framework, to target new programmable devices at AMD/Xilinx. These heterogeneous devices contain both general purpose ARM CPUs along with specialized AIEngine Vector/VLIW processors and Programmable Logic compute resources.

High-Level Programming Abstractions for GPGPU

Abstract

General-purpose computing on graphics processing units (GPGPU) is an approach to achieve highly parallel and energy efficient computing. While there are a lot of low-level programming techniques to exploit GPU's peculiar performance characteristics, it is challenging to write parallel programs for GPGPU. This talk introduces the speaker's attempts to bring high-level programming abstractions into GPGPU. In particular, it presents a support for objects and their dynamic allocation, and discusses further abstractions for task parallelism and graph-processing.

Towards Performance Portability and Correctness for HPC Systems

Abstract

Over the past decade, heterogeneous computing took over the leading role in HPC system design and has dominated the Top500 list. The complexity in heterogeneous systems introduces extreme challenges in application development and performance portability. Existing scientific applications require code modernization and transformation to make application porting possible. These transformations involve adopting new languages, programming models or performance portability layers to exploit new hardware features. Besides the challenges in application porting, the efforts required in development and debugging to ensure the correctness of the computation result increase significantly due to the massive parallelism in the heterogeneous HPC system.

In this talk, I will present how research and development activities in Lawrence Livermore National Laboratory (LLNL) assisted scientific application developments to overcome the challenges in performance portability and data race detection. Using cases from LLNL applications, I will present various strategies used at LLNL to pursue performance portability for the heterogeneous systems. I will also present how LLNL research tackles data races in multi-threaded parallel applications and how we assist the community in data race detection tool development.

Accelerating Data Computation with RISC-V Processors

Abstract

The open RISC-V architecture is leading the new wave of computing innovations, in particular for the emerging applications of AIoT, Automotive, 5G, Networking and Storage. Andes is the major force to take RISC-V mainstream and we would like to take this opportunity to share our vision and experience. In this talk, we will update the latest RISC-V architecture support and how they can accelerate data-intensive computation for a wide range of applications. The RISC-V Packed SIMD/DSP (P) extension targets for speeding up fixed-point computations for audio, voice, small image and slow video, usually in cost-sensitive and low-power devices. RISC-V Vector (V) extension aims for higher data-rate computations in both fixed-point and floating-point computations such as AI, communication, video and vision. For those interested in pursuing the ultimate performance efficiency with domain-specific architecture, RISC-V’s custom extensibility creates a whole new opportunity for innovations. A scalable architecture will be provided to highlight the important role a RISC-V processor can play.

To fulfill such a potential and reduce the development cycle, it is necessary to have easy-to-use software tools and an intuitive programming model, including advanced toolchains, processor pipeline visualizer/analyzer, and the optimized computation libraries for neural network, DSP and math functions. Furthermore, we will present a couple use cases in AI, NN, DSP applications, and results from several benchmarks.