Speakers

Technical Expertise:
- CPU and GPU compiler: optimizations, performance analyses
- HPC systems, programming languages and inter-disciplinary applications
Work Experience:
- Qualcomm: 2012
  - Director of Engineering: GPU compiler performance, test infrastructure and QA. Distributed team at San Diego, Santa Clara, India.
  - Project Lead: R&D on Halide for Adreno GPU
- Intel: 1999
  - GPU, OpenCL, C-for-media compilers
  - Speculative parallel threading
  - CPU compiler loop level optimizations, Itanium code generator
- Gintic Institute of Manufacturing Technology: 1997
  - Parallel discrete event simulation
- Defense Science Organization, Singapore: 1993
  - Parallel programming IDE, HPC applications
Education:
- PhD, 1993 Computer Science, University of California at Berkeley
- MSc, 1988, Computer Science, Stanford University
- BSc, 1988, Mathematical and Computational Sciences, Stanford University

Technical Areas:
- Architecture and HW/SW Interaction of Processors and SoCs
- SoC Design for Multimedia, Networking, and Domain-Specific Acceleration (DSA)
Experience: (in Silicon Valley before 2003)
- Andes Technology, 2005: Cofounder, CTO and SVP
- Faraday Technology, 2003: Principal Architect for ARM and DSP cores
- Afara/Sun, 2000: Senior Staff for Niagara T1000/T2000 processors, a 32/64-thread 8-core 64-bit Ultrasparc server-on-chip
- C-Cube, 1996: Director of Architecture/Validation for leading MPEG codec’s
- SGI/MIPS, 1993: Architecture/Verification group for 64-bit MIPS R10K (4-way out-of-order processor) and its follow-on
- Intergraph, 1991: Architecture group for Clipper C4 superscalar and C5 VLIW processors
Education:
- PhD, Computer Science, Univ. Illinois at Urbana-Champaign (UIUC)
- MS, Computer Science, National Tsing-Hua University (NTHU)
- BS, Electrical Engineering, National Taiwan University (NTU)

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