* First Author, # Corresponding Author
Hasna Nur Karimah*, Novi Prihatiningrum, Young-Ho Gong, Jonghoon Jin, and Yeongkyo Seo#, "Network Splitting Techniques and Their Optimization for Lightweight Ternary Neural Network," Electronics (ISSN: 2079-9292), vol. 14, no. 18, pp. 3651, Sep. 2025. (DOI: 10.3390/ELECTRONICS14183651)
Kon-Woo Kwon*, and Yeongkyo Seo#, "Hybrid Multi-Level Cell Spin-Orbit Torque Memory for Fast and Robust Memory Operations," IEEE Transactions on Nanotechnology (ISSN: 1941-0085), vol. 24, pp. 363-368, Jul. 2025. (DOI: 10.1109/TNANO.2025.3585167)
Hasna Nur Karimah*, Chankyu Lee, and Yeongkyo Seo#, "Batchnorm Free Binarized Deep Spiking Neural Network for a Lightweight Machine Learning Model," Electronics (ISSN: 2079-9292), vol. 14, no. 8, pp. 1602, Apr. 2025. (DOI: 10.3390/ELECTRONICS14081602)
Kyungseon Cho*, and Yeongkyo Seo#, "Energy-Efficient Hybrid Spin-CMOS Logic Design based on Cascadable Spin-Torque Majority Gate," IEEE Transactions on Magnetics (ISSN: 0018-9464), vol. 61, no. 1, pp. 4100108, Jan. 2025. (DOI: 10.1109/TMAG.2024.3494534)
Hyerim Kim*, Kon-Woo Kwon#, and Yeongkyo Seo#, "Complementary Polarizer SOT-MRAM for Low-Power and Robust On-Chip Memory Applications," Electronics (ISSN: 2079-9292), vol. 13, no. 17, pp. 3498, Sep. 2024. (DOI: 10.3390/ELECTRONICS13173498)
Muhammad Ismail*, Doohyung Kim, Eunjin Lim, Maria Rasheed, Chandreswar Mahata, Yeongkyo Seo#, and Sungjun Kim#, "Exploration of Analog Synaptic Plasticity and Convolutional Neural Network Simulation in Bilayer TiOxNy/SnOx Memristor for Neuromorphic Systems," ACS Materials Letters (ISSN: 2639-4979), vol. 6, no. 8, pp. 3514-3522, Aug. 2024. (DOI: 10.1021/ACSMATERIALSLETT.4C00406)
Juri Kim*, Subaek Lee, Yeongkyo Seo#, and Sungjun Kim#, "Emulating biological synaptic characteristics of HfOx/AlN-based 3D vertical resistive memory for neuromorphic systems," The Journal of Chemical Physics (ISSN: 0021-9606), vol. 160, no. 14, pp. 144703, Apr. 2024. (DOI: 10.1063/5.0202610)
Sureum Choi*, Daejin Han*, Chanyeong Choi, and Yeongkyo Seo#, "Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), vol. 32, no. 2, pp. 245-255, Feb. 2024. (DOI: 10.1109/TVLSI.2023.3336804)
Yeongkyo Seo*, and Kon-Woo Kwon#, "Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application," Electronics (ISSN: 2079-9292), vol. 12, no. 20, pp.4223, Oct. 2023. (DOI: 10.3390/ELECTRONICS12204223)
Yeongkyo Seo*, and Kon-Woo Kwon#, "High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAM," Micromachines (ISSN: 2072-666X), vol. 13, no. 12, pp. 2224, Dec. 2022. (DOI: 10.3390/MI13122224)
Sureum Choi*, Youngjun Jeon, and Yeongkyo Seo#, "High-Performance and Robust Binarized Neural Network Accelerator Based on Modified Content-Addressable Memory," Electronics (ISSN: 2079-9292), vol. 11, no. 17, pp. 2780, Sep. 2022. (DOI: 10.3390/ELECTRONICS11172780) - Editor’s Choice
Yunho Jang*, Gyuseong Kang, Taehwan Kim, Yeongkyo Seo, Kyung-Jin Lee, Byong-Guk Park, and Jongsun Park#, "Stochastic SOT device based SNN architecture for On-chip Unsupervised STDP Learning," IEEE Transactions on Computers (ISSN: 0018-9340), vol. 71, no. 9, pp. 2022-2035, Sep. 2022. (DOI: 10.1109/TC.2021.3119180)
Yeongkyo Seo*, and Kon-Woo Kwon#, "Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs," Electronics (ISSN: 2079-9292), vol. 10, no. 7, pp. 792, Apr. 2021. (DOI: 10.3390/ELECTRONICS10070792)
Yeongkyo Seo*, and Kon-Woo Kwon#, "Area-optimized design of SOT-MRAM," IEICE Electronics Express (ISSN: 1349-2543), vol. 17, no. 21, pp. 20200314, Nov. 2020. (DOI: 10.1587/ELEX.17.20200314)
Yeongkyo Seo*#, and Kaushik Roy, “High-Density SOT-MRAM Based on Shared Bitline Structure,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), vol. 26, no. 8, pp. 1600-1603, Aug. 2018. (DOI: 10.1109/TVLSI.2018.2822841)
Yeongkyo Seo*#, Xuanyao Fong, and Kaushik Roy, “Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), vol. 25, no. 4, pp. 1573-1577, Apr. 2017. (DOI: 10.1109/TVLSI.2016.2631981)
Yeongkyo Seo*#, Kon-Woo Kwon, Xuanyao Fong, and Kaushik Roy, “High Performance and Energy-Efficient On-Chip Cache using Dual Port (1R/1W) Spin-Orbit Torque MRAM,” IEEE Journal of Emerging and Selected Topics in Circuits and Systems (ISSN: 2156-3357), vol. 6, no. 3, pp. 293-304, Sep. 2016. (DOI: 10.1109/JETCAS.2016.2547701)
Yeongkyo Seo*#, Kon-Woo Kwon, and Kaushik Roy, “Area-Efficient SOT-MRAM with a Schottky Diode,” IEEE Electron Device Letters (ISSN: 0741-3106), vol. 37, no. 8, pp. 982-985, Aug. 2016. (DOI: 10.1109/LED.2016.2578959)
Yeongkyo Seo*#, Xuanyao Fong, Kon-Woo Kwon, and Kaushik Roy, “Spin Hall Magnetic Random-Access Memory with Dual Read/Write Ports for On-chip Caches,” IEEE Magnetics Letters (ISSN: 1949-3088), vol. 6, pp. 3000204, May. 2015. (DOI: 10.1109/LMAG.2015.2422260)
Yeongkyo Seo*#, Xuanyao Fong, and Kaushik Roy, “Domain Wall Coupling-Based STT-MRAM for On-Chip Cache Applications,” IEEE Transactions on Electron Devices (ISSN: 0018-9383), vol. 62, no. 2, pp. 554-560, Feb. 2015. (DOI: 10.1109/TED.2014.2377751)
Novi Prihatiningrum*, Jungu Kang, Chanyeong Choi, and Yeongkyo Seo#, "Design of an Area-Efficient and Error-Reduced CMOS Approximate Adder," International SoC Design Conference (ISSN: 2163-9612), Aug. 2024. (DOI: 10.1109/ISOCC62682.2024.10762587)
Hayun Bong*, Kyungseon Cho*, and Yeongkyo Seo#, "Automation Framework for Digital Circuit Design and Verification," International SoC Design Conference (ISSN: 2163-9612), Oct. 2022. (DOI: 10.1109/ISOCC56007.2022.10031431)
Taehwan Kim*, Eunjong Yeo, Yunho Jang, Yeongkyo Seo, Jongsun Park#, "Dynamic-Reference Based Early Write Termination for Low Energy SOT-MRAM," IEEE International Symposium on Circuits and Systems (ISSN: 2158-1525), Oct. 2020. (DOI: 10.1109/ISCAS45731.2020.9180877)