Research Area
High-speed serial link / Clock generation
Data converter (High-speed, High-resolution)
- In recent years, analog-to-digital converter (ADC) research has exhibited limited innovation, with most architectures gradually consolidating toward capacitor-array-based successive approximation register (SAR) ADCs. Although important advancements are still possible within this architecture, our vision extends beyond conventional paths, aiming instead toward revolutionary approaches emphasizing ADC density.
- The pursuit of smaller, more compact ADC solutions is critical across various technology domains, such as in-memory computing, high-speed wireline communications, advanced 5G/6G wireless systems, and sensor interface applications. Acknowledging these widespread demands, our lab is actively pioneering novel ADC architectures that prioritize high density combined with exceptional energy efficiency.
- At the heart of our exploration is the integration of conventional ADC design methodologies with our innovative capacitor-array-assisted charge-injection digital-to-analog converter (ciDAC) technology. This hybrid approach has the potential to substantially improve ADC density and performance, setting new benchmarks in multiple application scenarios.
- The incoming student will be tasked with spearheading these transformative architectural studies across several ADC configurations, including interleaved ADC, parallel ADC, and oversampling ADC structures. This role will involve in-depth research, design optimization, and validation of innovative ADC architectures, with a primary focus on achieving groundbreaking improvements in both density and energy efficiency.
Process in-memory computing
Biomedical circuits