International Journals
[Under preparation] Min-Jae Lee and Chan-Ho Kye, “XXX,” IEEE Access. (SCIE) - 28nm
[Under preparation] Chan-Ho Kye, “XXX,” IET EL. (SCIE)
[Under preparation] Jaekwang Yun and Chan-Ho Kye, “XXX,” IEEE TCAS-I. (SCIE) - 28nm
[Under preparation] Jaekwang Yun and Chan-Ho Kye, “XXX,” IEEE TIM. (SCIE)
[Under preparation] Chan-Ho Kye, Woo-Jin Jeon, and Jooyeol Rhee, “XXX,” IEEE TCAS-II. (SCIE) - 65nm
[Under preparation] Woo-Jin Jeon, Beom-Yeon Cho, and Chan-Ho Kye, “XXX,” IEEE TCAS-II. (SCIE) - 28nm
[Under revision] Chan-Ho Kye and Jaekwang Yun, “XXX,” IEEE Access. (SCIE)
Chan-Ho Kye, Daeho Yun, Jeonghyeon Han, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong, and Jooyeol Rhee, “A 48 Gb/s PAM-4 Transceiver with Transition Boosting and RLM Calibration for Next-Generation Memory Interface Testing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 34, no. 3, pp. 981-990, Mar. 2026. (SCIE, IF: 3.1, First author)
Hong-Seok Choi, Jae-Geon Lee, Seung-Hwan Gong, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Kwanseo Park, and Min-Seong Choo, “A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Seamless Frequency Detector in 40nm CMOS Technology,” IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 10, pp. 3602-3612, Oct. 2025. (SCIE, IF: 5.6, Co-author)
Chan-Ho Kye, Yu-Jin Byeon, Kyojin Choo, and Min-Seong Choo, “Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 11, pp. 4973-4984, Nov. 2024. (SCIE, IF: 5.2, First author)
Anhang Li, Hongyi Wu, Madhulika Lingamguntla, Ashbir Aviat Fadila, Chan-Ho Kye, Arvind Balijepalli, Johan Euphrosine, Tim Ansell, Nigel Coburn, Sachin Nadig, and Mehdi Saligane, “Integrated Multifunctional Laser-Induced-Graphene Sensor with an Open-Source AFE for Fast Prototyping of Flexible Wearables,” IEEE Solid-State Circuits Magazine (SSC-M), vol. 16, no. 2, pp. 49-57, Spring 2024. (SCOPUS, IF: 2.5, Co-author)
Chan-Ho Kye, Jihee Kim, Deog-Kyoon Jeong, and Min-Seong Choo, “A 4.5-to-14 GHz PLL-Based Clock Driver with Wide-Range 3-Shaped LC-VCOs for GDDR6 DRAM Test,” IEIE Journal of Semiconductor Technology and Science (JSTS), vol. 24, no. 3, pp. 284-288, Jun. 2024. (SCIE, IF: 0.5, First author)
Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, and Deog-Kyoon Jeong, “A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 67, no. 10, pp. 1814-1818, Oct. 2020. (SCIE, IF: 4.4, Co-author)
Chan-Ho Kye, Han-Gon Ko, Jinhyung Lee, and Deog-Kyoon Jeong, “A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 28, no. 5, pp. 1099-1106, May. 2020. (SCIE, IF: 2.8, First author)
Minho Choi, Chan-Ho Kye, and Deog-Kyoon Jeong, “Balancing scheme for phase current and flying-capacitor voltage in three-level DC-DC converter,” IET Electronics Letters (EL), vol. 56, no. 9, pp. 426-428, Apr. 2020. (SCIE, IF: 1.1, Co-author)
Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, and Deog-Kyoon Jeong, “A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator,” IEEE Solid-State Circuits Letters (SSC-L), vol. 2, no. 11, pp. 244-247, Nov. 2019. (SCIE, IF: 2.2, Co-author)
International Conferences(Oral)
Hong-Seok Choi, Jae-Geon Lee, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, and Min-Seong Choo, “A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Hiroshima, Japan, Nov. 2024. (Major Conference in IC Design, Co-author)
Chan-Ho Kye, Yu-Jin Byeon, Kyojin Choo, and Min-Seong Choo, “Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC,” IEEE International Symposium on Integrated Circuits and Systems (ISICAS), New Delhi, India, Oct. 2024. (First author)
Chan-Ho Kye and Kyojin Choo, “A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Haikou, China, Nov. 2023. (Major Conference in IC Design, First author)
Chan-Ho Kye, Jihee Kim, Kyungmin Baek, Kahyun Kim, Sangjin Pack, Changwon Jung, and Deog-Kyoon Jeong, “A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Taipei, Taiwan, Nov. 2022. (Major Conference in IC Design, First author)
Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, and Deog-Kyoon Jeong, “A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop,” IEEE Symposium on VLSI Circuits (VLSI-C), Kyoto, Japan, Jun. 2019. (Top Conference in IC Design, Co-author)
Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, and Deog-Kyoon Jeong, “A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, Feb. 2019. (Top Conference in IC Design, Co-author)
International Conferences(Poster)
Chan-Ho Kye, “Adaptive Time-Based Feedforward Equalizer in the Transmitter for the Next-Generation Memory Interfaces,” The 39th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Okinawa, Japan, Jul. 2024. (First author)
Chan-Ho Kye, Byung-Jun Kang, and Deog-Kyoon Jeong, “A 16-Gb/s injection-locked CDR in embedded clock receiver,” International Conference on Electronics, Information, and Communication (ICEIC), Hawaii, USA, Jan. 2018. (First author)
Patents
US 12,422,853, Test aid units, Oct. 2025.
US 11,423,963, Integrated circuit and memory, Aug. 2022.
[Applied] KR 10-2023-0039947, A test aid unit, Oct. 2024.
KR 10-2018-0169385, Integrated circuit and memory, Dec. 2018.