Research

My goal is to advance the semiconductor technology with more compact and efficient computing architecture and design automation system. So far, my work focused on the emerging devices to reduce the power consumption with unconventional computing. I am also interested in speeding up the chip design with AI-assisted electronic design automation (EDA).

Electronic Design Automation (EDA) is the core of integrated circuit (IC) industry. Both foundry and design company rely on EDA to support their business. A key component in EDA that bridges the foundry technology and IC design is device compact models. Modern compact models such as BSIM-CMG contain thousands of equations. When our devices keep scaling, more non-idealities show up and more model equations are required. It slows down the circuit simulation speed and the design for chips with billions transistors. As a first step, I introduced Artificial Intelligence (AI) into circuit design by developing next-generation transistor compact models using neural networks. By leveraging neural networks, thousands of device equations are replaced with efficient matrix computations, enabling faster simulation speeds compared to traditional compact models.   

• C. -T. Tung and C. Hu, "Neural Network-Based BSIM Transistor Model Framework: Currents, Charges, Variability, and Circuit Simulation," in IEEE Transactions on Electron Devices, vol. 70, no. 4, pp. 2157-2160, April 2023.

• C. -T. Tung, A. Pampori, C. Dabhi, S. Salahuddin and C. Hu, "A Novel Neural Network-based Transistor Compact Model including Self-Heating," in IEEE Electron Device Letters, vol. 45, no. 8, pp. 1512-1515, Aug. 2024.

• C. -T. Tung, S. Salahuddin and C. Hu, "BSIM-NN: A Machine Learning Compact Model for Fast IC Simulation," 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Hong Kong (Invited Talk).

• C. -T. Tung, M. -Y. Kao and C. Hu, "Neural Network-Based IV and CV Modeling with High Accuracy and Potential Model Speed," in IEEE Transactions on Electron Devices, vol. 69, no. 11, pp. 6476-6479, Nov. 2022.

• C. -T. Tung, S. Salahuddin and C. Hu, "Non-Quasi-Static Modeling of Neural Network-based Transistor Compact Model for Fast Transient, AC, and RF Simulations," in IEEE Electron Device Letters, vol. 45, no. 7, pp. 1277-1280, July 2024.

• C. -T. Tung, S. Salahuddin and C. Hu, "A SPICE-compatible Neural Network Compact Model for Efficient IC Simulations," 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Ferroelectric devices are solutions for future low power electronics due to its CMOS-compatibility, low energy consumption, and suitability for AI-driven architectures. It is suitable for in-memory and neuromorphic computing. To support the design of ferroelectric circuits, I studied the device physics and compact modeling of ferroelectric devices. The models developed accurately capture dynamics of ferroelectrics, multilevel switching, and are capable of designing the next generation electronic circuits. 

• C. -T. Tung, G. Pahwa, S. Salahuddin and C. Hu, "A Compact Model of Polycrystalline Ferroelectric Capacitor," in IEEE Transactions on Electron Devices, vol. 68, no. 10, pp. 5311-5314, Oct. 2021.

• C. -T. Tung, G. Pahwa, S. Salahuddin and C. Hu, "A Compact Model of Ferroelectric Field-Effect Transistor," in IEEE Electron Device Letters, vol. 43, no. 8, pp. 1363-1366, Aug. 2022.

• C. -T. Tung, G. Pahwa, S. Salahuddin and C. Hu, "A Compact Model of Metal–Ferroelectric-Insulator–Semiconductor Tunnel Junction," in IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 414-418, Jan. 2022.

• C. -T. Tung, S. Salahuddin and C. Hu, "A Compact Model of Antiferroelectric Capacitor," in IEEE Electron Device Letters, vol. 43, no. 2, pp. 316-318, Feb. 2022.

• C. -T. Tung, G. Pahwa, S. Salahuddin and C. Hu, "A Compact Model of Nanoscale Ferroelectric Capacitor," in IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4761-4764, Aug. 2022.

RRAM is another possible solution for in-memory computing and neuromorphic computing. I aimed to create a unified RRAM compact model that can describe the oxide-based RRAM (OxRAM) and the conducting bridge RAM (CBRAM) in one single framework. My study help improve the technology development for RRAM devices due to its complex and flexible material system.

• Chien-Ting Tung, Chetan Kumar Dabhi, Sayeef Salahuddin, and Chenming Hu, "A versatile compact model of resistive random-access memory (RRAM)," Solid-State Electronics, Volume 220, 2024, 108989.

MRAM is basically a binary memory unlike RRAM and FeFET. Therefore, it is more suitable for digital applications. The existing compact models of MRAM use 3D LLG equation or use simple marco models. They are either too time consuming or inaccurate. I developed a 1D LLG model that preserve the physical nature of LLG equation and can provide 2.5X speed improvement in circuit simulations. 

• C. -T. Tung, A. Dasgupta, H. Agarwal, S. Salahuddin and C. Hu, "A Compact Model of Perpendicular Spin-Transfer-Torque Magnetic Tunnel Junction," in IEEE Transactions on Electron Devices, vol. 71, no. 1, pp. 57-61, Jan. 2024, doi: 10.1109/TED.2023.3313997.