Nice to meet you!
Nice to meet you!
Information
Chenlin Shi, born in Beijing, China, 1998.
Contact Email: shi⭕hpc.is.uec.ac.jp
I am currently a Ph.D student living in Tokyo but will moved to Kobe in since April 2024 to join RIKEN R-CSS Processor Team as a JRA.
I like playing e-sports(MOBA) games and want to find co-players.
I like traveling around Japan.
Please enjoy the photos in the end of this page.
Research Background
China University of Mining & Technology, Beijing, China. B.E, Information Engneering, 2016~2020 (The major was canceled after I graduated...)
The University of Electro-Communications, Tokyo, Japan. M.E, Computer Engneering, 2021~2023
The University of Electro-Communications, Tokyo, Japan. Ph.D, Computer Engneering, 2023~
Research Interests
Computer Architecture
Reconfigurable Architecture
Hardware Design and Optimization (e.g., Systolic Array, (Approximate) multiplier/adder.)
Anything in Computer Architecture
Working Experience and Sholarship
Reseach Assistant, UEC, Tokyo, Japan, 2023.10~2024.3
JST Spring Researcher, UEC, Tokyo, Japan, 2023.10~2024.3
Reseach Assistant, UEC, Tokyo, Japan, 2024.5~
Junior Research Assosiate, RIKEN R-CCS, Kobe, Japan, 2024.4~
Research Experience
International Conference
C. Shi, T. Koizumi, R. Shioya, H. Yamaki, H. Honda, and S. Miwa, MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations, 2025 62nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation) (to appear).
C. Shi, B. Adhi, Lin Teng, S. Miwa, and K. Sano, Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI, 2025 62nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation) (to appear).
C. Shi, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, CNFET7: An Open Source Cell Library for 7-nm CNFET Technology, The 28th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.763-768, 2023 (acceptance rate: 102/328=31%).
C. Shi, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, Analysis of 64-bit Parallel Prefix Adders and 32-bit Matrix Multiply Units Designed with 7-nm CNFET, 2024 61st ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation).
C. Shi, B. Adhi, S. Miwa, and K. Sano, Post-Route Power Estimation: a Case Study of RIKEN-CGRA, 2024 IEEE International Conference on Cluster Computing (CLUSTER) (poster presentation).
Y. Aihara, B. Adhi, K. Aiyoshi, C. Shi, J. Anderson, T. Ueno, K. Sano and T. Miyajima, Impact of Reconvergent DFG Paths and Buffer Depth on Elastic CGRA Throughput, 2025 International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies(HEART2025).
B. Adhi, C. Shi, and K. Sano, Architecture Exploration of Heterogeneous CGRA Architecture for HPC and AI, The 7th R-CCS International Symposium (poster presentation).
Journal
C. Shi, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, CNFET-OCL: Open-source Cell Libraries for Advanced CNFET Technologies, IEEE Access, Vol.12, pp. 165335-165347 (2024).
MISC
C. Shi, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, CNFET7: An Open Source Cell Library for 7-nm CNFET Technology, IEICE VLD2022-92, pp.110-110 (2023)．
C. Shi，K. Sasaki, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, Evaluation of Microprocessors Placed-and-Routed with CNFET, IPSJ 2021-ARC-248, No.5, pp.1-6 (2022)．
Award
IEICE VLD Excellent Student Author Award for ASP-DAC 2023.
More
I am currently having interests about new-transistor-technologies-based VLSI circuits or processors, including CNFET, GAAFET, and seeking to find or develop new PDKs and cell libraries for academic uses.
I'd like to help develop PDKs and cell libraries, so if someone has the open-source resources and is willing to share or do an united research, please contact me.
I need help in developing SRAM cells. Please save me.