In this figure, the proposed adiabatic logic family circuit has been introduced. Here instead of constant supply voltage, we use a four-phase power clock that slowly charges and discharges the load capacitance of the logic circuit which in turn reduces the power dissipation. Here we are using the supply voltage of 1V taking an initial voltage of .2V which can be also called a constant DC voltage. By varying the rise time and fall time we can change the evaluation phase and recover phase and according to the change of evaluation and recover phase we can further decrease the power dissipation until they are smaller than the product of RC.Here like normal CMOS we are using a pull-up P1 and pull-down N1. Below the N1 we are using another N2 whose gate is connected with the four power supply voltage and it is parallel to newly connected P2 whose gate is connected to the ground. Here in this case a positive ground of 0.2 voltage is connected. The length and width of P2 should of same size of N2.Here when the voltage rises from 0.2V to 1V, the output capacitor is being charged slowly. This is called the evaluation phase. Again, when the power clock goes from 1V to .2V then the output capacitor has higher power than the power clock supply so some of the power will go back to the power clock. This phase is known as the recovery phase. Thus, adiabatic processes will be maintained. Here the gate of N2 is connected by the power clock supply. So, it changes the current flow supply in N2. In the voltage of 1V, almost full current will be flown from N2. As the current flow in P2 is two times slower than N2 meaning it has higher resistance, less current will be flown from P2. Also, the gate of P2 is connected to .2V. As a result, the P2 is not fully on at any time having more resistance in P2 than usual. So, almost all current will flow from N2 when power supply is on hold state. In voltage close to the threshold voltage, less current will be flown from N2. So, with the change of current, the power dissipation can be manipulated. However, due to the change of current flow, sometimes the output may appear in a degraded state. This is also one of the many reasons, a PS2 is being attached in parallel so it can minimize the output degradation. Also, PMOS2 being used in pull-down will create a finite voltage [23]. So, when the power clock supply reaches .2V. The finite voltage of .2 in the ground and PMOS2 will be higher than the power clock supply for a brief moment. So, it will slightly reverse biases in the whole circuit and the leakage power will be reduced [24].Here unlike conventional CMOS, the power rises from .2 to 1 voltage rather than 0 to 1 voltage. So, the time taken for the output to change concerning input is lower than the conventional CMOS. Thus, propagation delay is also reduced.