Embedded Files
Simultaneous Read-Write Operation of New Low-Power SRAM with Memristor Acting as Resistance
Description: This SRAM is compared among 6T,7T,8T, and 10T and result shows that it consumes less power than those SRAMs. It is done in 16nm, 22nm,32nm & 45nm HP PTM model.
NMOS-Based New Low Power SRAM
Description: This SRAM is compared among 6T,7T,9T, and 10T, and the result shows that it consumes less power than those SRAMs.It is done in 16nm HP PTM model. The run time is 100 ns
Strong Vdd SRAM with PMOS as Footer for Low Power Performance.
Description: This SRAM is compared to 6T,7T,9T, and 10T, and the result shows that it consumes less power than those SRAMs.It is done in a 16nm HP PTM model. The run time is 100 ns. Here, Pull-Up PMOS in SRAM works in near-threshold voltage, so it will get VDD but take low power. Also, a footer PMOS gives weak "0".So the whole circuit works from Vdd to Vdd-Vth. As a result, it provides less power.
Buffer Based New Adiabatic Circuit
Description: This simulation is done in 16nm HP PTM model. The pull up network is connected to NMOS and the pull down network is connected to PMOS. In the same way, other digital logics can be simulated.It consumes less than 90% of the power
Modified ECRL Circuit for Low Power Consumption
Description: It is done in 16nm HP PTM model.Two extra PMOS are connected to reduce the power.
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