Research Interests

As on-chip power consumption becomes the most critical barrier, we need disruptive technology solution such as silicon photonics that can scale in capacity and reduce power footprint while delivering scalable bandwidth. Photonic interconnects can provide high interconnect bandwidth by combining multiple wavelengths, provide minimal access latencies, and high power-efficiency that remains independent of capacity and distance for on-chip communications. In this research, we explore several aspects of utilizing photonics for NoCs such as power-efficiency, programmability, cache coherence, reliability, bandwidth reconfiguration, technology exploration and heterogeneity. 

A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy-efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. Manually

designing rules for optimizing such competing trade-offs is likely to require a substantial engineering effort, which, in turn, is bound to result in suboptimal solutions, given the combinatorial size of the decision space and the complexity of the interactions between decisions made for various NoC components. Machine Learning (ML) techniques can work with high dimensional inputs and can be used to automatically infer complex decisions in order to optimize designs. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs.

With the explosion of computing devices and systems in everyday consumer  electronics, the amount of energy required to power information and computing technologies (ICT) is reaching close to 5% of worldwide carbon emissions . Therefore, efforts at improving the sustainability of computing systems are fast becoming an existential threat to society and will require substantial efforts. Sustainability in computing should be based on three universally accepted tenets – reuse, reduce and recycle – of hardware components and systems. While operational energy has significantly scaled down, embodied energy is dramatically increasing which indicates that there is a need for a more balanced approach with trade-offs in power, performance, and reliability. In this research, we propose to improve the sustainability of computing systems via three tenets of reuse, recycle and reduce by exploiting the advances in electro-optic fabric to design resilient, multi-function architectures and accelerators that effectively balance performance, power, reliability, and sustainability via cross-layer optimization. 

With each technology generation, security concerns for integrated circuits (IC) will continue to grow as malicious attackers find new ways to compromise critical computing systems. As aggressive transistor scaling continues according to Moore's law, the ability to detect any malicious alterations which is achieved by additional transistors/circuits will become more difficult with each technology generation. As multicores require NoC architectures to meet communication requirements, NoCs should provide security measures to protect sensitive data from fault injection attacks between IP cores while ensuring functional correctness to prevent systems from failing.

Unlike Artificial Neural Networks (ANNs) that use tensors to communicate between processing elements (that have multiply and accumulate units), neuromorphic systems communicate using spikes in a Spiking Neural Network (SNN) that computes due to their spatio-temporal encoding of information. Typically, spikes communicate across a tile-based or a grid-based architecture, where each tile implements the neurons and synapses in a crossbar configuration.  In this research, we propose a modular and reproducible toolchain for mapping SNNs onto NoC-based neuromorphic platforms.