Post date: Nov 18, 2015 8:34:10 PM
Title: Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers
Authors: Amro Awad (NCSU), Pratyusa Manadhata (HP Labs), Yan Solihin (NCSU), Stuart Haber (HP Labs), William Horne (HP Labs)
Abstract: As non-volatile memory (NVM) technologies are expected to replace DRAM in the near future, new challenges and de- sign constraints should be considered when architecting NVM- based systems. For example, NVMs have slow and power- consuming writes, and limited write endurance. Thus, reducing the number of writes is highly desirable. Similarly, NVMs have a data remanence vulnerability, i.e., they retain data for a long time after being powered off. NVM encryption alleviates the vulnerability, but exacerbates limited endurance by increasing the number of writes to memory. In this paper, we propose an approach to reduce the number of writes to encrypted NVMs. We observe that in current systems a large percentage of all main memory writes can result from data shredding in operating systems, which is the process of zeroing out physical pages before mapping them to new processes, in order to protect previous processes’ data. Our Non-Volatile Main Memory controller, Silent Shredder, re- purposes initialization vectors used in standard counter mode encryption to completely eliminate the writes occurring due to data shredding. Furthermore, it speeds up reading shredded cache lines, and hence reduces power consumption and improves overall performance. We discuss several use cases, including virtual machines’ data isolation and user-level large data initialization, where Silent Shredder can be used effectively at no extra cost. To evaluate our design, we use gem5, a detailed full-system simulator, to run 3 graph analytics applications from the PowerGraph framework and 26 multi-programmed workloads from the SPEC 2006 benchmark suite. Silent Shredder eliminates an average of 48.6% of the writes in the initialization and graph construction phases. Furthermore, it speeds up main memory reads by 3.3 times on average, and improves the number of instructions per cycle (IPC) by 6.4% on average.