Academic projects
Summary:
- A new class of three phase multilevel inverters with optimized structures
- Structural optimization of three-phase multilevel inverters with respect to PWM strategy used for common mode voltage elimination
- Novel Multilevel single-phase Inverter Topologies for Low Common Mode Voltage and Leakage Current for Transformerless Grid Connected Applications
A new class of three phase multilevel inverters with optimized structures
Abstract: The goal of this project is to optimize the structure of three phase multilevel inverters (MLI) and have a retrofit capability with which a simple 3-level inverter can be converted to n-level inverter. The proposed optimizations aim to reduce the device count of a 3-ϕ, MLI. This is achieved by cascading a level generation converter with a T-type MLI. Depending on the configuration of the level generation converter, two 3-ϕ, MLI structures are proposed. The working of the proposed topologies are verified using simulation and experimental investigation.
Structural optimization of three-phase multilevel inverters with respect to PWM strategy used for common mode voltage elimination
Abstract: Common mode voltage (CMV) is a serious problem in inverter systems which can be eliminated using multilevel inverters and operating it using the zero CMV (ZCMV) space vector (SV) locations. This method is known is ZCMV space vector modulation (SVM). However, this renders an MLI capable of operating higher number of levels to be operated at lower number of levels as all the SV locations are not used. In this project, MLI structures are optimized with respect to the ZCMV SVM scheme, eliminating the unused SVs from the output SV hexagon of the proposed MLI topologies. Simulation models and hardware prototypes of the proposed topologies are built to verify the operation.
Novel Multilevel single-phase Inverter Topologies for Low Common Mode Voltage and Leakage Current for Transformerless Grid Connected Applications
Abstract: The small rooftop PV systems of less than 5kW are becoming popular because of their ease of implementation. For this kind of applications, single-phase transformerless inverters prove their superiority because of their size, cost, and good efficiency. To further reduce the filter size, it has been tried to add the multi-level feature. But, this brought different issues such as incomplete multi-level performance, continuous source disconnection, the inability of generating reactive power, the effect of switch terminal capacitance in TCMV, and reduced dc-bus utilization. This project attempts to address all of these issues simultaneously by proposing a family of new topologies and developing their working hardware prototype.