resume

My resume in PDF can be obtained here

ARINDAM BASU

Assistant Professor, Division of Circuits & Systems,

School of Electrical and Electronic Engineering

S2.2-B2-31, 50 Nanyang Avenue, Singapore 639798.

E-mail : arindam.basu@ntu.edu.sg, arindam.basu@gmail.com

EDUCATION

January 2006 - April 2010

Georgia Institute of Technology, Atlanta, Georgia

Ph.D. in Electrical and Computer Engineering

Thesis: Neural Dynamics in Reconfigurable Silicon

Advisor: Dr. Paul Hasler

January 2006 - April 2009

Georgia Institute of Technology, Atlanta, Georgia

M.S. in Mathematics

• GPA : 4.00 / 4.00

July 2000– May 2005

Indian Institute of Technology, Kharagpur, India

M. Tech and B.Tech. (Hons.) in Electronics and Electrical Communication Engineering

• GPA : 9.5/ 10.00 (Rank 1st overall in the institute)

WORK EXPERIENCE

January 2006 - Present

Georgia Institute of Technology, Atlanta, Georgia

Graduate Research Assistant, CADSP Laboratory

Research Projects:

• Mathematical and Electronic modeling of neural dynamics and bifurcations.

• Programmable analog IC for Signal Processing, Neural Modeling and Interfacing.

• Design of interface for on-chip tuning of a reconfigurable IC.

• Wide dynamic range interface circuits for ultrasonic, hearing-aid and imaging applications.

May2008 – Aug 2008

Texas Instruments, Dallas, Texas

Co-Op, Nanometer Analog Integration Group, Wireless Division

• Design of LNA input matching network and automatic tuning scheme for FM

applications.

-Designed input matching network for LNA in 65nm for different antenna impedances. Developed a novel automatic tuning scheme and associated circuits for reconfiguring

matching network to counter changes in antenna impedance.

May 2003 -July 2003

Georgia Institute of Technology, Atlanta, Georgia

Summer Internship

Research Projects:

• Design and testing of programmable log-domain filter IC.

• Printed circuit board design for testing Vector Matrix Multiplier IC.

TEACHING EXPERIENCE

Fall 2007

Summer 2008

Fall 2009

ECE 4823: Nonlinear Dynamics in IC Design (Georgia Tech.)

Delivered Lectures on Dynamics based electronic design of ion-channels in neuron models.

Workshop on Programmable Analog Circuits (Univ. of Southern California, Telluride, MITRE)

Conducted laboratory sessions on programmable circuits using an FPAA (Field Programmable Analog

Array) developed at Georgia Tech.

ECE 6435: Neuromorphic Analog VLSI Circuits (Georgia Tech.)

Responsible for preparing and delivering lectures and supervising laboratory work.

TEACHING INTERESTS

Analog/ Digital circuits and systems. Nonlinear Dynamics/ Differential Equations.

VLSI : analog and digital. Bio-inspired/Neuromorphic circuits.

Communication theory. Signals and Systems.

TECHNICAL PROFICIENCIES

• CAD Tools : Cadence ICFB simulator, Virtuoso layout editor, HSPICE, Calibre, Assura, Allegro.

• Software : MATLAB, Maple, Verilog, VHDL, C

AWARDS & ACHIEVEMENTS

• Recipient of Prime Minister of India Gold medal from IIT Kharagpur in 2005 that is awarded to the student with the highest GPA in the outgoing batch of Dual-Degree(B.Tech+M.Tech) students.

• Best Student Paper Award at IEEE Ultrasonics Symposium, 2006.

• Best Live Demonstration Award at ISCAS, 2010

• Best Student Paper finalist at ISCAS, 2008.

• Participant in Telluride Neuromorphic workshop in 2009.

• National Talent Search Scholar (India).

• Jagadis Bose National Talent Search Scholar (India).

• Order of Merit , IIT Kharagpur (2005).

• Ranked 4th in state level engineering entrance at 10+2 level out of approximately 100,000 students.

SERVICE

Member of IEEE since 2007.
Reviewer for ISCAS and TCAS-I.

PUBLICATIONS

Some of the important publications are listed here. A more detailed list can be found here.

Journal

A. Basu, R. Robucci, and P. Hasler, “A Low-power, Compact, Adaptive Log-TIA operating over Seven decades of current,” IEEE Trans. on Circuits and Systems-I, vol. 54, no. 10, pp. 2167-2177, Oct 2007.
A. Basu, C. Petre and P. Hasler, “Dynamics and Bifurcations in a Silicon Neuron,” accepted to IEEE Trans. on Biomedical Circuits and Systems.
A. Basu, S. Ramakrishnan, C. Petre, S. Koziol, S. Brink and P. Hasler,“Neural Dynamics in Reconfigurable Silicon,” accepted to IEEE Trans. on Biomedical Circuits and Systems.
A. Basu and P. Hasler, “A Fully Integrated Architecture for Fast and Accurate Programming of Floating-gates,”accepted to IEEE Trans. on VLSI.
A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan, et.al, “A Floating-gate based Field Programmable Analog Array,” accepted to IEEE Journal of Solid State Circuits.
A. Basu and P. Hasler, “Nullcline based design of Silicon Neurons,” accepted to IEEE Trans. on CAS I.
S. Suh, A. Basu, C. Schlottmann, P. Hasler and J. Barry, “Low-Power Discrete Fourier Transform for OFDM: A Programmable Analog Approach,” accepted to IEEE Trans. on CAS I
S. Peng, M. Qureshi, P. Hasler, A. Basu and F. L. Degertekin, “A Charge-Based Low-Power High-SNR Capacitive Sensing Interface Circuit,” IEEE Trans. on Circuits and Systems-I, vol. 55, no. 7, pp. 1863-72, Aug 2008.

Conference

A. Basu, C. Twigg, S. Brink, P. Hasler et.al, “RASP 2.8: A New Generation of Floating-gate based Field Programmable Analog Array,” in Proc. of IEEE Custom Integrated Circuits Conference, pp. 213-16, Sept. 2008, San Jose, USA.
A. Basu, Shubha Ramakrishnan and P. Hasler,“Neural Dynamics in Reconfigurable Silicon,” accepted to ISCAS 2010.
A. Basu, C. Petre and P. Hasler, “Bifurcations in a Silicon Neuron,” in Proc. of IEEE Intl. Symposium on Circuits and Systems, pp.428-431, May 2008, Seattle, USA. (Finalist, Best Student Paper)
A. Basu and P. Hasler, “A fully integrated architecture for fast programming of Floating-gates,” in Proc. of IEEE Intl. Symposium on Circuits and Systems, pp. 957-960, May 2007, New Orleans, USA.
A. Basu, K. Odame and P. Hasler, “Dynamics of a Logarithmic Transimpedance Amplifier,” in Proc. of IEEE Intl. Symposium on Circuits and Systems, pp. 1673-1676, May 2007, New Orleans, USA.
A. Basu, A. Mal and A.S. Dhar, “Digital controlled analog architecture for DCT and DST using capacitor switching,” in Proc. of IEEE Intl. Symposium on Circuits and Systems, Vol. 2, pp. 309-312, May 2004, Vancouver, Canada.
A. Basu, R. Robucci, and P. Hasler, “A Low-power, Compact, Adaptive Log-TIA operating over Seven decades of current” in Proc. of IEEE Intl. Symposium on Circuits and Systems, pp. 3055-3058, May 2007, New Orleans, USA.
A.Basu and A.S. Dhar, “Design Issues in Switched Capacitor Ladder Filters,” in Proc. of IEEE International Conference on VLSI Design, pp. 862-865, Jan 2005, Kolkata, India.
B. Marr, A. Basu, S. Brink and P. Hasler, ”A Learning Digital Computer,” to appear in Proc. of the Design Automation Conference (DAC), July 2009.
S. Peng, M Qureshi, A. Basu et al., “Floating-Gate Based CMUT Sensing Circuit Using Capacitive Feedback Charge Amplifier,” in Proc. of IEEE Ultrasonics Symposium, Oct. 2006, Vancouver, Canada. (Best Student Paper)
S. Peng, G. Gurun, C. Twigg, M. Qureshi, A. Basu et.al, "A Large Scale Reconfigurable Smart Sensory Chip," accepted to IEEE Intl. Symposium on Circuits and Systems, 2009.

Patents Filed

A. Basu and P. Hasler, "Systems and methods for improved floating-gate transistor programming," USPTO Patent Application 20090323425, filed in 2009.
A. Basu, S. Ramakrishnan and P. Hasler, "FPAA for Implementing Neuron Dynamics," Invention Disclosure ID 5190, 2010.

Books

P. Cvitanovic, R. Artuso, R. Mainieri, G. Tanner and G. Vattay, Chaos: Classical and Quantum, http://chaosbook.org/, contributed figures, tables and exercises.

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