Publications

Journal

(First author *, Corresponding author ^)

1. S. Park*, A. Hemelhof, Y. Zhang, G. Gramegna, and P. Wambacq, "D-Band Doubler and Quadrupler", (Under Review), 2025.

2. S. Park*, Y. Zhang, A. Hemelhof, K. Vaesen, M. Ingels, and P. Wambacq, "D-Band LNA", (Under Review), 2025.

3. D. Kim, S. Park^, S. Kim, "DPD in Nonlinear RF Systems", (Under Review), 2025.

4. Y. Zhang, K. Vaesen, G. Mangraviti, K. Y. Kapusuz, S. Park, M. Glassee, S. Lemey, P. Wambacq, and G. Gramegna, "A 56 Gbps Zero-IF D-Band Beamforming Transmitter", (Accepted, IEEE Transactions on Microwave Theory and Techniques (T-MTT)), 2025.

5. S. Balasubramanian, K. Vaesen, A. Kankuppe, S. Park, and C. Wulff, "A D-Band 13-mW Dual-Mode CMOS LNA for Joint Radar–Communication in 22-nm FD-SOI CMOS," IEEE Solid-State Circuits Letters, vol. 7, pp. 259-262, 2024.

6. M. Park, J. Jin, S. Park and J. Chun, “The Design of Non-Stacked and Symmetric XOR for High-Speed Applications,” Electronics Letters, vol. 59, no. 13, 2023. 

7. A. Kankuppe, S. Park, K. Vaesen, D.-W. Park, B. van Liempd, S. Sinha, P. Wambacq, and J. Craninckx, “A 67 mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 7, pp. 1982-1996, 2022.

8. S. Park*, D.-W. Park, K. Vaesen, A. Kankuppe, S. Sinha, B. van Liempd, P. Wambacq, and J. Craninckx, “A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 7, pp. 2114-2129, 2022.

9. A. Kankuppe, S. Park*^, P. T. Renukaswamy, P. Wambacq, and J. Craninckx, “A Wideband 62-mW 60-GHz FMCW Radar in 28-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques (T-MTT), vol. 69, no. 6, pp. 2921–2935, 2021.

10. S. Park*^, X. -Q. Du, M. Grözing and M. Berroth, “Design of a 0.13 µm SiGe Limiting Amplifier with 14.6 THz Gain-Bandwidth-Product,” Advances in Radio Science, vol. 15, pp. 115-121, 2017.

Conference

1. A. Hemelhof, S. Park, Y. Zhang, M. Ingels, G. Gramegna, K. Vaesen, D. Yan, P. Wambacq, "A D-band Power-Combined Stacked Common-Base Power Amplifier Achieving 20.9 dBm Psat and 24.3 % PAE in a 250-nm InP HBT Technology," 2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Oct. 2024, pp. 185-188.

2. Y. Zhang, K. Vaesen, G. Mangraviti, S. Park, Z. Zong, P. Wambacq and G. Gramegna, "A 56Gb/s Zero-IF D-Band Transmitter for a Beamformer in 22nm FD-SOI," 2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2024, pp. 347-350.

3. E. Martens, A. Cooman, P. Renukaswamy, S. Nagata, S. Park, J. Lagos, N. Markulic, J. Craninckx, "22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC," 2024 IEEE International Solid-State Circuits Conference (ISSCC), February 2024, pp. 396-398.

4. D. Yan, S. Park, Y. Zhang, M. Ingels, P. Wambacq, “A Compact K-band, Asymmetric Coupler-based, Switchless Transmit-Receive Front-end in 0.15 µm GaN-on-SiC Technology,” in 2023 IEEE European Solid-State Circuits Conference (ESSCIRC), September 2023, pp. 457-460.

5. D. Yan, S. Park, Y. Zhang, D. Peumans, M. Ingels, P. Wambacq, “A Differential GaN Power Amplifier with < 1° AM-PM Distortion for 5G mm-wave Applications,” in European Microwave Integrated Circuits Conference (EuMIC), September 2023, pp. 80-83.

6. A. Kankuppe, S. Park, K. Vaesen, D.-W. Park, B. van Liempd, P. Wambacq, and J. Craninckx, “A 67 mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28 nm CMOS,” in IEEE European Solid-State Circuits Conference (ESSCIRC), September 2021, pp. 471-474.

7. S. Park, D. Park, K. Vaesen, A. Kankuppe, B. van Liempd, P. Wambacq, and J. Craninckx, “A 135-155 GHz 9.7%/16.6% DC-RF/DC-EIRP Efficiency Frequency Multiply-by-9 FMCW Transmitter in 28 nm CMOS”, in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2021, pp. 15-18.

8. S. Park, A. Kankuppe, P. Renukaswamy, D. Guermandi, A. Visweswaran, J. C. Garcia, S. Sinha, P. Wambacq, and J. Craninckx, “A 62 mW 60GHz FMCW radar in 28 nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2020, pp. 31–34.

9. P. Renukaswamy, N. Markulic, S. Park, A. Kankuppe, Q. Shi, P. Wambacq and J. Craninckx, “A 12mW 10GHz FMCW PLL based on an Integrating DAC with 90kHz rms frequency error for 23MHz/μs slope and 1.2GHz Chirp Bandwidth”, IEEE International Solid-State Circuits Conference (ISSCC), pp. 278-280, February 2020.

10. X. -Q. Du, M. Grözing, A. Uhl, S. Park, F. Buchali, K. Schuh, S. T. Le, and M. Berroth, “A 112-GS/s 1-to-4 ADC front-end with more than 35-dBc SFDR and 28-dB SNDR up to 43-GHz in 130-nm SiGe BiCMOS”, 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019, pp. 215-218, June 2019.

11. S. Park, X. -Q. Du, M. Grözing and M. Berroth, “Design of a High-Speed Limiting Amplifier in a 0.13 µm SiGe BiCMOS Technology,” Kleinheubacher Tagung, Miltenberg, Germany, September 2016.

12. S. Park, Y. Jang and D. Yoon, “Parameter Estimation of Symbol Unit Convolutional Interleaver,” The 35th Conference of Korea Institute of Information and Communication Engineering, vol. 18, no. 01, pp. 557-560, May 2014.