G. Heo, Y. Chang, Y.-U. Jeong, J. Yun, J. Lee, and S. Kim, "An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface," in 2025 IEEE Custom Integrated Circuits Conference (CICC), April 2025.
Y.-U. Jeong, and J.-H. Chae, "Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces," IEEE Transactions on Instrumentation and Measurement (TIM), vol. 73, pp. 1-8, December 2024.
Y.-U. Jeong, and J.-H. Chae, "A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 12 , pp. 6306-6315, December 2024.
S.-H. Jeong, Y.-U. Jeong, and S. Kim, "An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 71, no. 11, pp. 4628-4632, November 2024.
J. Yun, S. Lee, J. Kim, J.-H. Chae, S. Kim, and Y.-U. Jeong, "A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces," IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 9 , pp. 2971-2982, September 2024.
G. Kim, Y. Chang, Y.-U. Jeong, and S. Kim, "A 8Gb/s PAM-4/NRZ Dual-Mode Transmitter for Panel Interfaces with Run-length Limited Maximum Transition," in IEEE 37th International System-on-Chip Conference (SOCC), September 2024.
S. Seo, Y.-U. Jeong, J. Yun, J. Kim, and S. Kim, "A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces," in IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.
Y.-U. Jeong, S. Choi, S. Kim, and J.-H. Chae, "Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 12 , pp. 4793-4803, December 2023.
Y.-U. Jeong, J.-H. Chae, and S. Kim, "A 0.85-pJ/b 16-Gb/s/pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces," IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 9 , pp. 2659-2667, September 2023.
H. Park, Y.-U. Jeong, and S. Kim, "A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces,” IEEE Access, vol. 10, pp. 91888-91896, 2022.
S. Lee, Y.-U. Jeong, J. Yun, J.-H. Chae, and S. Kim, "A Low-Power DRAM Transmitter with Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching," IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II), vol. 69, no. 11, pp.4208-4212, November 2022.
J.-H. Chae, Y.-U. Jeong, and B.-Du. Choi, "Design and Comparative Study of Voltage Regulation-based 2-tap Flexible Feed-forward Equalizer for Voltage-mode Transmitters,” IEEE Access, vol. 10, pp. 37446-37456, 2022.
Y.-U. Jeong, S. Choi, J.-H. Chae, J. Yun, S.-H. Jeong, and S. Kim, " A 10 Gb/s/pin Single-Ended Transmitter with Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces," IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 69, no. 3, pp.1125-1134, March 2022.
S. Choi, Y.-U. Jeong, J.-H. Chae, S.-H. Jeong and S. Kim, "A Differentiating Receiver with a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface,” IEEE Access, vol. 9, pp. 120285-120296, 2021.
C. Hyun, Y.-U. Jeong, S. Kim, and J.-H. Chae, "An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation," Electronics, 10, 1768, July 2021.
H. Park, J. Park, J. W. Lee, Y.-U. Jeong, S.-H.Jeong, S. Kim, and J.-H.Chae, "A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces," in IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
Y.-U. Jeong, H. Park, C. Hyun, J.-H. Chae, S.-H. Jeong, and S. Kim, "A 0.64-pJ/bit 28-Gb/s/pin High-Linearity Single-Ended PAM-4 Transmitter with an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface," IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 4, pp. 1278-1287, April 2021.
J. Yun, S. Lee, Y.-U. Jeong, S.-H. Jeong, and S. Kim, "A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction," in IEEE Asian Solid-State Circuits Conference (ASSCC), November 2020.
Y.-U. Jeong, J. Park, M. Kim, J.-H. Chae, J. Yun, H. Lee, and S. Kim,"A 9Gb/s Wide Output Range Transmitter with 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces," IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II), vol. 67, no. 9, pp.1589-1593, September 2020.
Y.-U. Jeong, H. Park, C. Hyun and S. Kim, " A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ calibration for Memory Interfaces," in IEEE Symposia on VLSI Technology & Circuit (SOVC), June 2020.
J.-H. Chae, Y.-U. Jeong, and S. Kim, "Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces," IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 67, no. 9, pp.2972-2983, September 2020.
Y.-U. Jeong, J.-H. Chae, S. Choi, J. Yun, S.-H. Jeong, and S. Kim, "A Low-Power Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm CMOS," in IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2019.
J. Park, J.-H. Chae, Y.-U. Jeong, J.-W. Lee, and S. Kim, "A 2.1-Gb/s 12-Channel Transmitter with Phase Emphasis Embedded Serializer for 55-inch UHD Intra-panel Interface," IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 10, pp. 2878-2888, October 2018.
J. Park, J.-H. Chae, Y.-U. Jeong, J.-W. Lee, and S. Kim, "A 2.1Gbps 12-Channel Transmitter with Phase Emphasis Embedded Serializer for UHD Intra-panel Interface," in IEEE Asian Solid-State Circuits Conference (ASSCC), November 2017.
J.-H. Chae, M. Kim, H. Ko, Y. Jeong, J. Park, G.-M. Hong, D.-K. Jeong, and S. Kim, "266-2133 MHz Phase Shifter using All-Digital delay-locked loop and Triangular-Modulated Phase Interpolator for LPDDR4X Interface," IET Electronics Letters (EL), vol. 53, no. 12, pp. 766-768, June 2017.