Research

Journals:

1. A. Kumar, A. Singh, and A. Kumar, "Signal integrity analysis of Cu-CNT based shield DM-TGV using temperature and roughness-aware EM-RA technique for 3D integration," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2025.3648614. 

2. A. Kumar, A. Kumar, and A. Singh, “Frequency- and time-domain analysis of shield differential multibit TGV using EM-RA technique for 3D integrated circuits,” Microelectronics Journal, vol. 168, Art. no. 107014, Feb . 2026, DOI: 10.1016/j.mejo.2025.107014. 

3. A. Singh, A. Kumar, and A. Kumar, "Signal integrity analysis in mixed CNT bundle interconnects using EM-RA," Journal of Computational Electronics, vol. 24, no. 127, Jun. 2025. DOI: 10.1007/s10825-025-02353-y .

4. A. Kumar and B. K. Kaushik, “Exponential matrix - rational approximation (EM-RA) model for SWCNT bundle and hybrid Cu-CNT interconnects,” IEEE Transactions on Electromagnetic Compatibility, vol. 63, no. 4, pp. 1212–1222, Aug. 2021, DOI: 10.1109/TEMC.2020.3037204.

5. A. Kumar and B. K. Kaushik, “Edge and dielectric surface roughness-aware EM-RA model for MLGNR interconnects,” IEEE Transactions on Nanotechnology, vol. 20, pp. 567-575, Jun. 2021, DOI: 10.1109/TNANO.2021.3093174.

6. A. Kumar and B. K. Kaushik, "Edge-roughness aware EM-RA model for signal integrity analysis in MLGNR interconnects," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 2, pp. 273-283, Feb. 2021, DOI: 10.1109/TCPMT.2020.3043198.

7. A. Kumar, V. R. Kumar, and B. K. Kaushik, “Transient analysis of crosstalk induced effects in mixed CNT bundle interconnects using FDTD technique,” IEEE Transactions on Electromagnetic Compatibility, vol. 61, no. 5, pp. 1621–1629, Oct. 2019, DOI: 10.1109/TEMC.2018.2872899.

8. A. Kumar and B. K. Kaushik, “Transient analysis of graphene-based on-chip interconnects using closed-form MRA model,” Semiconductor Science and Technology (IOP Science), vol. 36, no. 6, pp. 065014-065031, May 2021, DOI: 10.1088/1361-6641/abf905.

9. A. Kumar and B. K. Kaushik, “Transient Analysis of Hybrid Cu-CNT On-Chip Interconnects Using MRA Technique,” IEEE Open Journal of Nanotechnology, vol. 3, pp. 24-35, 2022, DOI: 10.1109/OJNANO.2021.3138344.

10. R. Kumar, A. Kumar, S. Guglani, S. Kumar, S. Roy, B. K. Kaushik, R. Sharma, and R. Achar, “A temperature and dielectric roughness-aware matrix rational approximation model for the reliability assessment of copper- graphene hybrid on-chip interconnects,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 9, pp. 1454–1465, Sep. 2020, DOI: 10.1109/TCPMT.2020.3004414. 

Conferences:

1. A. Nagar, S. Barot, and A. Kumar, "An optimized 90nm CMOS PLL with reduced power consumption and locking time," 2025 IEEE 4th International Conference for Advancement in Technology (ICONAT), Goa, India, 2025, pp. 1-4, DOI: 10.1109/ICONAT66879.2025.11362871.

2. K. Desai, A. Kumar, and A. Kumar, "Efficient chip design of penta linear array charge coupled device (CCD)," 2024 IEEE 1st International Conference on Electronics, Communication and Signal Processing (ICECSP), New Delhi, India, 2024, pp. 1-4, DOI: 10.1109/ICECSP61809.2024.10698328. 

3. A. Kumar and D. K. Jarwal, "Efficient high-gain operational amplifier design for Σ-Δ ADCs in VLSI," 2023 IEEE 2nd International Conference on Futuristic Technologies (INCOFT), Belagavi, Karnataka, India, 2023, pp. 1-7, DOI: 10.1109/INCOFT60753.2023.10425580. 

4. V. Doshi and A. Kumar, "Design and development of time and memory-efficient video translation tool," 2023 IEEE 4th International Conference for Emerging Technology (INCET), Belgaum, India, 2023, pp. 1-4, DOI: 10.1109/INCET57972.2023.10170354. 

5. A. Kumar, "Accurate resistance modeling of Cu-CNT ULSI interconnects," in 2023 IEEE International Conference for Advancement in Technology (ICONAT), Goa, India, 2023, pp. 1-4.

6. A. Kumar, B. K. Kaushik, S. Roy, and R. Achar, “Crosstalk analysis in MWCNTs using a closed-form matrix rational approximation technique,” in Proc. IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Montreal, QC, Canada, Oct. 2019, pp. 1–3, DOI: 10.1109/EPEPS47316.2019.193210.

7. A. Kumar and B. K. Kaushik, “Impact of MWCNT radii on the performance of nano regime interconnects,” in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Chandigarh, India, Dec. 2018, pp. 1-3, DOI: 10.1109/EDAPS.2018.8680886.

8. A. Kumar, V. Nehra, and B. K. Kaushik, “Time-domain finite-difference based analysis of induced crosstalk in multiwall carbon nanotube interconnects,” in Proc. SPIE, Nanoengineering: Fabrication, Properties, Optics, and Devices XIV, San Diego, California, USA, Aug. 2017, pp. 103540Q.1-8, DOI: 10.1117/12.2273816.

9. S. Guglani, A. Kumar, R. Kumar, B. K. Kaushik, R. Sharma and R. Achar, and S. Roy, “Temperature-aware closed-form matrix rational approximation model for crosstalk analysis of multi-walled carbon nanotube interconnects,” in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Kaohsiung, Taiwan, Dec. 2019, pp. 1–3, DOI: 10.1109/EDAPS47854.2019.9011623.

10. R. Kumar, S. Pathania, S. Guglani, A. Kumar, S. Kumar, S. Roy, B. K. Kaushik, and R. Sharma, “Role of grain size on the effective resistivity of Cu-graphene hybrid interconnects,” in Proc. IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, June 2020, pp. 1620–1625, DOI: 10.1109/ECTC32862.2020.00254.

Book Chapter:

1. S. Joshi, A. Kumar, and B. K. Kaushik, “Paradigm shift of on-chip interconnects from electrical to optical,” in Noise Coupling in System-on-Chip, 1st ed., Florida, USA: CRC Press, 2018, pp. 401–444.