Research
The direction of arrival prediction using asymmetric surface structures
We propose an asymmetric surface structure-equipped photodetector capable of sensing the direction of arrival of the photon in addition to standard photon detection. We present a detailed FDTD Lumerical simulation-based surface structure design optimization for precise detection of the incidence angle (θ) and angle of azimuth (Φ). The presence of the surface structures facilitates an asymmetric electromagnetic (EM) wave interaction in the case when the light is introduced orthogonal to the structures versus when it is parallel to the structures (i.e., change in Φ results in a change in the responsivity). Similarly, due to the variation in the path length of the EM wave with the θ, the responsivity varies. Using the detailed absorption profile simulated for a range of wavelengths, θ and Φ, and the function regression model, we have devised a method to predict the direction of arrival, i.e., θ and Φ. The model in the current state works accurately for θ: 10-80°, and Φ: 0-90°. Such direction-sensitive photodetectors in combination with function regression models can revolutionize the field of short-range wireless data communication, light-detection and ranging, object tracking, and indoor positioning.
High-speed PiN photodiode design space exploration to break the speed-efficiency trade-off
We propose a PiN device design method addressing the speed-efficiency trade-off to enable independent optimization of speed and absorption efficiency. We present a hybrid device structure combining lateral and vertical PiN architectures. We introduce a highly doped buried P-region connecting the top P-contact doping and separating the N-contact doping by a critical width. The top P- and N- contacts are separated by a lateral i-layer for absorption. A lateral i-layer enables a larger volume for efficient photon absorption, and a highly doped P-region enables an efficient collection of slow-moving holes after the illumination is turned off. The critical i-layer width sandwiched between the buried P-region and the N-contact doping facilitates an efficient conduction path. We optimize the critical width (optimized width = 200 nm) for device capacitance and the admittance to maximize the response time (rise time, fall time, and full-width half maxima). The optimization is performed using ATLAS Silvaco technology computer-aided design software. The optimized device structure possesses 22 GHz 3 dB bandwidth (BW = 0.35/Fall-time) at 850 nm illumination wavelength.
The angle of incidence independent detection using PT-equipped APDs
Introducing the photon-trapping microholes (PTMH) features into the avalanche photodiode (APD) reduces the angle of incidence dependency in the electromagnetic (EM) wave absorption. We calculated the external quantum efficiency (EQE) of the flat APD and compared it with that of the PTMH-equipped APD for two different angles of incidence, e.g., 45° and 30°. The inset of Fig. (a) demonstrates the path-length change from l₁ to l₂ for θ₁ and θ₂ angles of incidence. The inset of Fig. (b) plots the ∆EQE highlighting a systematic right shift in the oscillating EQE profile with the angle of incidence change from 45° to 30°. Figures (c) and (d) show the EQE profile of a PTMH-equipped device with 45° and 30° angles of incidence. The systematic shift in the oscillating EQE profile present in the flat device has been diluted with the introduction of PTMH. The presence of PTMH creates a perturbation in the EM wave travel path and disrupts the resonance phenomenon as shown in the inset of Fig. (c). The ∆EQE profiles at both 45° and 30° angles of incidence for the PTMH-equipped device are shown in the inset of Fig. (d). Adding PTMH interrupts the resonance phenomenon and resolves the incidence angle dependency of the EM wave absorption. This dilution eliminates the need for additional lenses and diffractive optics for aligning the incident EM waves, a common practice in current imaging technologies.
Silicon avalanche photodiodes
Our study outlines a technique for developing a sub-10 V Si-APD. We used the Silvaco Atlas TCAD simulator to optimize the doping profile of the APD to achieve the desired electric field and enable sub-10 V breakdown. We then grew the APD stack epitaxially and fabricated Si-APDs. To improve absorption efficiency, we incorporated a photon-trapping micro-hole (PTMH) array into the devices. The designed devices had a breakdown voltage of around 8.0 V and a low dark current of approximately 30 pA for a 25 μm diameter device, even with the PTMH structures. We achieved a high multiplication gain (M) of 296.2 at 850 nm with 10 μW laser power. The incorporation of PTMH resulted in an approximately 5-fold increase in EQE at 850 nm, and this enhancement was uniformly distributed across the wavelength range from 640−1100 nm. The smooth SOI interface caused a prominent resonance to occur at certain wavelengths, resulting in an oscillatory EQE profile for the flat device. The EQE profile in the flat device also showed a strong dependency on the illumination direction, which was circumvented by introducing the PTMH array. The devices we fabricated showed excellent sensitivity, gain, and dark current performance, surpassing most of the performance parameters reported in the state-of-the-art literature.
MQW-based Infrared photodiodes
Due to the indirect bandgap nature of Si, despite all the infrastructural compatibility, it is yet to even be comparable to the III-V semiconductors. The applications where absorption efficiency cannot be compromised, the III-V semiconductors come to the rescue. We are working on multi-quantum-well near-infrared (NIR) photodetectors which can be used for numerous applications such as medical diagnostics, IR-based satellite imaging, remote sensing, etc. The low NIR wavelength is benign for human eyes and muscle cells and has the potential to capture in-depth real-time body-organ images. The work is still ongoing. More information will be added as and when the results are out.
Process Induced Variability (PIV) Modeling
I worked on analytically modeling the process-induced variability (PIV) such as line-edge-roughness, metal-gate-granularity, random-dopant-fluctuations, etc., for advanced logic transistors such as FinFET, Nanosheet FET, and Nanowires FET. As the logic transistors shrink, the device feature size has become comparable to the PIVs. There are many process technologies to suppress the PIVs, but they are not effective enough to protect the devices from variability. Circuit designers require an accurate device model to predict the circuit-level performance to enable mass production. Our model is accurate and purely analytical to be incorporated into the existing SPICE models and enables a variability-aware circuit performance prediction.
Experimental Validation of PIV Model
Having a compact and accurate device model is a boon for circuit designers. By incorporating our analytical PIV model into the BSIM-CMG SPICE platform, we devised a fully functional compact model for FinFET. We collaborated with IMEC, Leuven for their 14-28nm FinFET experimental data to validate our model. Our model shows an excellent agreement with the experimental data for a large range of lengths and widths.
Proposed NSFET Device Architecture
NSFETs are the recent most logic transistors invented by IBM in 2017. The NSFET is shown to have a higher drive current per device footprint compared to FinFET, and better gate control due to the gate-all-around nature of the gate stack. In all the logic transistors nitride spacers are added to isolate the source/drain contact from the gate contact. Due to the stacked nature of the channel in NSFET, nitride isolations are added in between the sheets as well. Due to the presence of the inner spacers, during the regrowth of the source/drain regions, the channel stress is compromised, which leads to reduced mobility and therefore reduced drive current. We present a structural modification by removing the inner spacers. Removing the inner spacers facilitates continuous epitaxial growth of the source and the drain region, and the channel stress remains intact. We show that despite an increase in the intrinsic device capacitance, an increase in mobility results in a 36% reduction in the intrinsic resistance-capacitance delay of the device.
Single crystalline Gd₂O₃ deposition
Silicon-on-insulator (SOI) technology is an attractive improvement over bulk-Si-based devices mainly for RF applications where the substrate parasitics play a major role in deciding the off-state leakage and intrinsic device capacitance. However, the high manufacturing cost of the SOI wafers inhibits the usage of the technology. We propose an alternative to the soitec's SmartCut process. We propose to replace the amorphous SiO₂ buried oxide layer with a single crystalline Gd₂O₃ layer and enable a layer-by-layer deposition of the active Si layer. Gd₂O₃ is proven to have a compatible surface energy and lattice mismatch with Si(111) orientation. We demonstrate a single crystalline Gd₂O₃ deposition at high temperature in a radio-frequency (RF) sputter system, a high-volume manufacturing compatible deposition tool. We show a gradual phase transfer of Gd₂O₃ from mono-clinic to cubic with the RF power modulation. Such single crystalline Gd₂O₃ layers have the potential to replace the SiO₂ buried oxide layer and enable a layer-by-layer growth of Si on Crystalline (X'lline) Oxide (SOXI).
Germanium on X'lline Oxide (GeOXI)
We used the crystalline Gd₂O₃ as a buried oxide and deposited Germanium on it to demonstrate layer-by-layer manufacturing of Ge-on-X'lline oxide (GeOXI) wafers. We deposit amorphous Germanium at room temperature on the crystalline Gd₂O₃, followed by a cap Gd₂O₃ layer at a high temperature. The increased temperature crystallizes the amorphous Germanium layer and the Gd₂O₃ cap layer prevents the Germanium mobility on the surface. The process is known as solid phase epitaxy (SPE). Using the SPE process, we successfully demonstrate a single crystalline Germanium layer formation on the crystalline Gd₂O₃.