Introduction

I am working as a postdoctoral fellow with Prof. M Saif Islam at the University of California, Davis in the Department of Electrical Engineering and Computer Sciences. I am working on the design, simulation, and fabrication of visible and infrared photodetectors using Group-IV and III-V semiconductors. My expertise lies in semiconductor device design, fabrication, simulation, modeling, photon-trapping features driven light-matter interaction manipulation, material growth and characterization, and superlattice quantum well-based bandgap engineering. I have acquired a detailed understanding of fundamental device physics, light-matter interaction, electromagnetics, device fabrication, electrical and structural characterization, and device simulation and analytical modeling.

I have completed my Ph.D. in microelectronics from the Department of Electrical Engineering at IIT Bombay, India. I started my professional career right after graduation from the Department of Electrical Engineering at IIT Patna, India, in 2013. I spent two years working on Static Random Access Memory (SRAM) design at Masamb Electronics PVT. LTD, Noida, India. I utilized Virtuoso and IC Design as schematic and layout editors for SRAM bit-cell designing and ELDO and HSPICE for pre- and post-layout simulations. Eventually, I worked on memory design automation using memory compilers facilitated by ST-microelectronics. This experience gave me a strong hold on CMOS logic circuit designing and technology tape-outs.

Later, in 2015, I joined the Ph.D. program in the Department of Electrical Engineering, at IIT Bombay, India, and started working with Prof. Udayan Ganguly. During my Ph.D., I worked on process-induced variability (PIV) modeling for advanced logic devices, such as FinFET, Nanosheet FET (NSFET), and Nanowire FET. I worked on modeling line edge roughness (LER) and combining the impact of metal gate granularity with LER to develop a variability-aware BSIM-CMG  platform for SPICE simulation at sub-10nm technology nodes. Prior work experience enabled me to incorporate the PIV mathematical model into the SPICE framework. Further, I validated the developed PIV-aware SPICE platform using 14-28 nm FinFET experimental data in collaboration with IMEC, Leuven, Belgium. In parallel, I developed a process to fabricate a low-cost silicon-on-insulator wafer essential for radio frequency (RF) and photonic applications. The proposed process is a layer-by-layer deposition of buried oxide (BOX) and semiconducting layer on a bulk-Si, as opposed to a complex Smart Cut™ process. I proposed to replace the SiO₂ BOX layer with a crystalline Gd₂O₃ layer and deposit the Silicon or Germanium layer on the Gd₂O₃ using the solid phase epitaxy technique (SPE). First, I optimized the growth of cubic Gd₂O₃ in a high-temperature ambiance in an RF-sputter system to show a gradual phase transfer of Gd₂O₃ from monoclinic to cubic by modulating the RF power. Further, I demonstrated the single crystalline Germanium growth on crystalline Gd₂O₃ by using SPE.

After Ph.D., I joined IMEC as a researcher and developed a process design kit (PDK) for 3nm, 5nm, and 7nm technology nodes for FinFETs and NSFETs. I also worked in collaboration with Huawei to propose a novel NSFET device architecture to tackle channel stress loss during the source/drain epitaxial regrowth. We proposed replacing the inner nitride spacers used to isolate the gate and source/drain between the nanosheets with a continuous single crystalline silicon layer of graded doping. Doing so prevents stress loss, increases channel mobility, and leads to an increased drive current. A continuous silicon path increases the thermal conductivity and reduces the self-heating of the device.

After a year of experience at IMEC, I decided to switch to academia and join Prof. Saif Islam's group as a postdoctoral fellow. Currently, I am working on the design and fabrication of Si-avalanche photodetectors and III-V-based multi-quantum well photodetectors for visible and near-infrared light detection. These standard high-performance photodiodes when combined with the photon-trapping (PT) feature result in exceptionally high absorption efficiency, along with a significant reduction in the device capacitance. Along with the enhanced performance, I have experimentally demonstrated the absorption spectra modulation by changing the dimensions of the PT features.

Such elaborate first-hand exposure to device modeling, simulation, fabrication, and circuit designing has equipped me with keen eyes for detailed device physics and a broader bottom-up device-circuit-to-system level implementation of an idea. Insofar, I have filed two patents and published 21 research papers. I have volunteered as a guest lecturer for Electromagnetic Theory, and Semiconductor Device Fabrication courses running at UC Davis. I have volunteered to organize the INSPIRE summer workshop co-organized by UC Davis and CITRIS. I am a frequent reviewer of IEEE and APL journals and participated in the Postdoctoral Research Symposium review process at UC Davis.