Achievement

Journal (1st Author)

[28] J. Lee, E. Hwang, I. Myeong*, and G. Kim*, "Integration of Volatile and Non-Volatile Memory for Enhanced Synaptic Devices"IEEE Transactions on Electron Devices. (SCIE, IF :3.221) (In Writing)

[27] J. Choi, E. Oh, and I. Myeong*, "Channel IL Engineering in FeVNAND for Multi-level Operation: Balancing E-Field Distribution and Grain-Induced Current margin degradation", IEEE Transactions on Electron Devices. (SCIE, IF :3.221) (In Writing)

[26] J. Kim, and I. Myeong*, "Co-Optimization of Back Gate Biasing and Wordline Control for Enhanced Reliability in FeVNAND", IEEE Transactions on Electron Devices. (SCIE, IF :3.221) (In Writing)

[25] C. Lim, D. Kang, and I. Myeong*, "Study on Self-Heating of CFET in Cryogenic Environment and Its Impact on PPAC” IEEE Access (SCIE, IF: 3.1) (In Writing)

[24] Y. Shin, D. Kwon*, and I. Myeong* "The Impact of Through Silicon Metal (TSM) contact on bottom P type Multi bridge channel FET in CFET" IEEE Electron Device Letter (SCIE, IF: 4.98) (In Writing)

[23] Y. Kim, and I. Myeong*, “Advantages of Ferroelectric VNAND from the perspective of Hot Carrier Injection” IEEE Electron Device Letter (SCIE, IF: 4.98) (In Writing)

[22] J. Kim, I. Song* and I. Myeong*,  “An Analytical Effective Mobility Model of Polycrystalline Silicon Channel”, Applied Physics Letter, 2025. (SCIE, IF: 3.1) (Under Review)

[21] J. Jung, J. Kim, I. Myeong*, and I. Song*, “Accurate RF CMOS Channel Thermal Noise Model Including Parasitic Source/Drain Resistance” Elsevier Results of Physics, 2025. (SCIE, IF: 5.3) (Under Review)

[20] J. Kim, S. Lee, and I. Myeong*, “Enabling Scalable Ferroelectric based Future Generation Vertical NAND Flash with Bonding-Friendly Architecture: Strategies for Erase and Disturb Optimization ”, RCS Nanoscaele, 2025. (SCIE, IF :5.1) (Under Review) 

[19] H. Jo, S. Lee, and I. Myeong*, “Vacuum-Based Spacer Architecture for Enhanced Reliability in Scaled 3D NAND Flash Memory” IEEE Transaction on Electron Device (SCIE, IF: 3.221) (Major Revision)

[18] J. Lee, T. Kim, A. Ildefonso, A. Khachatrian, D. McMorrow, M.-K. Cho, J. D. Cressler, I. Myeong*, and I. Song*, “Design of Robust Clock-Tree for Soft Error Recovery”, IEEE Transaction on Aerospace and Electronic Systems, 2025. (SCIE, IF: 5.1) (Under Review)

[17] I. Myeong, S. Shin and I. Song, “Physics-based Compact Modeling of Advanced 3D nanoscale Vertical NAND Flash Memory”, Wiley Advanced Science, 2025. (SCIE, IF :15.1) (JCR: 5.78%) (Under Review)

[16] M. Kim, Y. Shin, D. Ha*, and I. Myeong*., “Direct Backside Contact Impact on 3-dimensional Stacked FET SRAM Beyond 1nm Node”, IEEE Journal of Electron Device Society, 2025. (SCIE: 2.23) (Under Review)

[15] C. Lim, I. Myeong*, “ A Compact Model for GIDL-assisted Erase Transients of 3D MONOS Charge-Trap NAND Flash Memories”, Wiley Advanced Theory and Simulation, 2025. (SCIE: 3.1) (Under Review)

[14] Y. Shin, B. Kwak, I. Myeong*, and D. Kwon*, “The Impact of Through Silicon Metal(TSM) contact on Performance and thermal reliability in CFET.” IEEE Electron Device Letter, 2025. (SCIE, IF: 4.98)

[13] H. Kim, I. Myeong*, S. Kim, S. Hong, S. Kim, W. Kim, D. Ha, and D. Kim., “Influence of Bulk Trap Properties in HfO2- Based Ferroelectric Layers on the Transient Dynamics of Ferroelectric Field-Effect Transistors”, IEEE Transaction on Electron Devices, 2025. (SCIE, IF :3.221)

[12] M. Kim, I. Myeong, J Park, S. Park, D. Yeon, D. Ha, and H. Shin., “Development of SRAM in 3-dimensional Stacked FET with Direct Backside Contact Beyond 1nm Node” IEEE Transaction on Nanoelectronics, 2025. (SCIE, IF :2.91)

[11] J. Jeong, I. Myeong*, and I. Song*, “Mitigation of Single-Event Transistors in High-Frequency Analog Circuits Using Choke Inductors”, Elsevier Nuclear Engineering and Technology, 2025. (SCIE, IF: 2.8)

[10] I. Myeong and I. Song, “Self-Heating-Based Channel Thermal Noise of Advanced Sub-5-nm node Nanoplate FET”, Elsevier Results in Physics, 2024. (SCIE, IF :5.3)

[09] I. Myeong, H. Kim, W. Kim, D. Ha, S. Ahn, J. Song, “A Comprehensive Study of Transient Characteristics in FeFET using in-situ Vt measurement method”, IEEE Electron Device Letter, 2024. (SCIE, IF :4.98) (Editor's pick and main cover)

[08] I. Myeong, H. Kim, S. Kim, S. Lim, K. Kim, W. Kim, D. Ha, S. Ahn, J. Song, “Strategies for a Wide Memory Window of Ferroelectric FET for Multilevel Ferroelectric VNAND Operation”, IEEE Electron Device Letter, 2024. (SCIE, IF :4.98)

[07] I. Myeong and H. Shin, “Study on self-heating effect and lifetime in vertical-channel field effect transistors”, Elsevier Miroelectronics Reliability, 2021. (SCIE, IF :2.1)

[06] I. Myeong, I. Song, M. Kang, H. Shin, “Self-Heating and Electrothermal Properties of Advanced Sub-5-nm node Nanoplate FET”, IEEE Electron Device Letter, 2020. (SCIE, IF :4.98)

[05] I. Myeong, J. Kim, H. Ko, I. Song, Y. Kim, H. Shin, “A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Model”, IEEE Transaction on Computer Aided Design and Systems, 2020. (SCIE, IF :2.9)

[04] I. Myeong, D. Son, H. Kim, H. Shin “Analysis of Self Heating Effect in DC/AC Mode in Multi-Channel GAA-Field Effect Transistor”, IEEE Transaction on Electron Devices, 2019. (SCIE, IF :3.221)

[03] I. Myeong, D. Son, H. Kim, M. Kang, J. Jeon, H. Shin, “Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing Ioff in Various Sub-10-nm 3-D Transistors”, IEEE Transaction on Electron Devices, 2019. (SCIE, IF :3.221)

[02] I. Myeong, D. Son, H. Kim, M. Kang, H. Shin, “Analysis of Self Heating Effect according to Buried Oxide Thickness in SOI Nanowire FET”, IEIE Journal of Semiconductor Technology and Science, 2017. (SCIE, IF :0.6)

[01] I. Myeong, D. Son, H. Kim, M. Kang, H. Shin, “Analysis of Self-Heating Effect on vertical FET according to Shallow Trench Isolation”, Elsevier Solid State Electronics, 2017. (SCIE, IF :1.91)

Journal (Co-Author) 

[07] E. Hwang, I. Myeong, and G. Kim, "A p-n Junction Gate DRAM for Non-Destructive and Linear Synaptic Modulation in Neuromorphic Computing " AIP Advances (SCIE, IF : 2.0) (Under review)

[06] S. Tayal, B. Smaani, S. Rahi, A. Kumar, S. Bhattacharya, J. Ajayan, B. Jena, I. Myeong, B-G. Park, Y. Song, “Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for SRAM-Based Cache Memory Applications”, IEEE Transaction on Electron Devices, 2022. (SCIE, IF :3.221)

[05] H. Kim, D. Son, I. Myeong, J. Park, M. Kang, J. Jeon, H. Shin, “Optimization of Stacked Nanoplate FET for 3-nm Node”, IEEE Transaction on Electron Devices, 2020. (SCIE, IF :3.221)

[04] H. Kim, D. Son, I. Myeong, D. Ryu, J. Park, M. Kang, J. Jeon, H. Shin, “Strain Engineering for 3.5-nm Node in Stacked-Nanoplate FET”, IEEE Transaction on Electron Devices, 2019. (SCIE, IF :3.221)

[03] D. Ryu, I. Myeong, J. Lee, M. Kang, J. Jeon, H. Shin, “Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device”, IEEE Transaction on Electron Devices, 2019. (SCIE, IF :3.221)

[02] H. Kim, I. Myeong, D. Son, M. Kang, J. Jeon, H. Shin, “Analysis on Self-Heating Effect in Three-Stacked Nanoplate FET”, IEEE Transaction on Electron Devices, 2018. (SCIE, IF :3.221)

[01] D. Son, I. Myeong, H. Kim, M. Kang, J. Jeon, H. Shin,  “Analysis of ELectrothermal  Characteristics of GAA Vertical Nanoplate-Shaped FETs”, IEEE Transaction on Electron Devices, 2018. (SCIE, IF :3.221)

Conference (1st Author)

[11] I Myeong et al., "CFET optimization for high performance and reliability....", IEEE VLSI, 2026. (Preparing for Submission)

[10] I Myeong et al., "Optimization of 2D/Ferroelectric Hybrid Gate Stack for FeFET-based 3D FeVNAND and PIM Applications", IEEE VLSI, 2026. (Preparing for Submission) 

[09] I. Myeong, S. Lim, T. Kim, S. Park, S. Noh, “A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND”, IEEE IRPS, 2024. (Top conference)

[08] S. Lim, I. Myeong, T. Kim, S. Park, S. Noh, “Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND”, IEEE IEDM, 2023 (Top conference)

[07] I. Myeong, M. Kang, J. Jeon, H. Shin, “Analysis of Self Heating Effect in Vertical-channel Field Effect Transistors”, IEEE EuroSimE, 2019. (Invited talk)

[06] I. Myeong, M. Kang, M. Kang, H. Shin, “Analysis of DC Self Heating Effect in Stacked Nanosheet Gate-All-Around Transistor”, IEEE EDTM, 2018.

[05] I. Myeong, M. Kim, H. Kim, D. Son, D. Ryu, M. Kang, H. Shin, “Analysis of Self Heating Effect characteristi cs for DC / AC bias in multi-channel Nanowire-Field Effect Transistor”, AWAD, 2018

[04] I. Myeong, D. Son, H. Kim, M. Kang, H. Shin, “Thermal-aware Shallow Trench Isolation design in Bulk/SOI FinFET and Vertical FET considering off current”, KCS, 2018

[03] I. Myeong, D. Son, H. Kim, M. Kang, H. Shin, “Analysis of Self-Heating Effects in Vertical MOSFETs According to Device Geometry”, IEEE SNW, 2018

[02] I. Myeong, D. Son, H. Kim, M. Kang, H. Shin, “Analysis of Self Heating Effect according to Insulator thickness in SOI Nanowire FET”, ICSPD, 2017.

[01] I. Myeong, D. Son, H. Kim, M. Kang, H. Shin, “Analysis of Self Heating Effects on vertical FET according to Shallow Trench Isolation”, ISDRS (IEDM satellite conference), 2016.

Conference (Co-Author)

[10] G. Kim, H. Cho, H. Shin, S. Lee, S. Lee, Y. Nam, M. Jung, I. Myeong, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, J. Ahn, and S. Jeon, “ In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling”, IEEE VLSI, 2024. (Top conference)

[09] T. Kim, S. Lim, I. Myeong , S. Park, S. Noh, “Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET”, IEEE IRPS, 2024. (Top conference)

[08] M. Kang, I. Myeong, K. Fobelets, “Geometrical influence on Self Heating in Nanowire and Nanosheet FETs using TCAD Simulations”, IEEE EDTM, 2020.

[07] J. Kim, I. Myeong, M. Kim, S. Kim,  M. Kang, J. Jeon, H. Shin, “Modeling of Channel Current in Sub-threshold Region for Poly-Si based Macaroni Structure in 3D NAND Flash Memories”, IEEE EDTM, 2019.

[06] M. Kim, I. Myeong, J. Kim, M. Kang, J. Jeon, H. Shin, “BSIM-CMG Modeling for 3D NAND Cell with Macaroni Channel”, IEEE EDTM, 2019.

[05] H. Kim, D. Son, I. Myeong, M. Kang, H. Shin, “Analysis on Self Heating Effects in Nanowire FET Considering Effective Thermal Conductivity of BEOL”, IEEE SNW, 2018.

[04] D. Son, I. Myeong, M. Kang, H. Shin, “In-depth analysis of self-heating effects in vertical nanoplate-shaped GAAFETs”, IEEE SNW, 2018.

[03] D. Son, I. Myeong, M. Kang, H. Shin, “Analysis of Self Heating for GAA Vertical Nanosheet–shaped FETs in Single transistor and Digital circuit”, KCS, 2018

[02] H. Kim, D. Son, I. Myeong, M. Kang, H. Shin, “Analysis on Self Heating Effect in Nanowire FET Considering Accurate Thermal Conductivity”, ICSPD, 2017.

[01] D. Son, I. Myeong, H. Kim, M. Kang, H. Shin, “Analysis of Self-Heating Effects in Vertical FET”, ICSPD, 2017.

Patent 

[17] PN 정션 게이트 메모리 셀 및 이를 포함하는 반도체 메모리 (2025-1-113-KR )

[16] 반도체 메모리 장치 및 이를 포함하는 전자 시스템 (내용: 백게이트 강유전체 플래시 소자의 읽기 방해를 줄일 수 있는 새로운 읽기 동작 방식), (출원번호: P20240072041)

[15] 반도체 장치 및 데이터 저장 시스템 (내용: 수직 적층형 낸드 메모리 장치와 제조 방법), (출원번호:P20240060281)

[14] 반도체 소자 및 이를 포함하는 전자 시스템 (내용: Ferro VNAND의 MINFIS 구조에서 trap Nitride내 N농도 구배), (출원번호: P20240029858)

[13] 메모리 소자 (내용: Ferro VNAND에서의 ON Mold 높이 제작 규칙), (출원번호: P20240016206)

[12] 반도체 소자 및 이를 포함하는 데이터 저장 시스템 (내용: Ferro VNAND의 Peripheral circuit에 적용하기위한 vertical 채널을 가지는 MOSFET), (출원번호: P20240018837)

[11] 비휘발성 메모리 장치 및 이의 동작 방법 (내용: Ferro VNAND의 동작 속도를 Boosting하기 위한 New IPSS operation scheme), (출원번호: P20230124275)

[10] 반도체 소자 (내용: FeVRAM CELL 면적을 최대로 활용하는 3D-FEFET WL PAD 형성 방법), (출원번호: US18/170136)

[09] 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템  (내용: 강유전체 저장 층과 완전히 채워진 채널 구조를 가지는 트라이 게이트 수직 낸드), (출원번호: P20230107620)

[08] 반도체 메모리 장치 및 그를 포함하는 전자 시스템, (내용: Laminate를 적용한 FeVNAND에서 T-모양을 가지는 BL Pad 제작 방법), (출원번호: US18/587355)

[07] 반도체 장치 및 이를 포함하는 전자 시스템 (내용: Memory Window 및 동작 속도 향상을 위한 Ferroelectric VNAND MI(ONO)FS Gate 적층 구조),(출원번호: US18/658265)

[06] 반도체 장치 및 이를 포함하는 전자 시스템 (내용: Cylindrical Ferroelectric VNAND에서 Multi Level 구동), (출원번호: US18/655488)

[05] 반도체 장치 및 이의 제조 방법, 그리고 반도체 장치를 포함하는 전자 시스템 (내용: Memory Window  개선 및 charge 유입 개선을 위한 FeVNAND 신구조), (출원번호: US18/732268)

[04] 반도체 장치 및 이의 제조 방법, 그리고 반도체 장치를 포함하는 전자 시스템 (내용: GIDL ERS 개선을 위한 FeVNAND 변경 구조), (출원번호: P20230139554)

[03] 반도체 장치 및 이의 제조 방법, 그리고 반도체 장치를 포함하는 전자 시스템 (내용: Gate 전압 boosting 및 산포 개선을 위한 신구조 FeVNAND), (출원번호: P20230245243)

[02] 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템 (내용: 동작 전압 및 Ferro 특성을 개선한 FeVNAND 변경 구조), (출원번호: US18/601009)

[01] 반도체 장치 및 이의 제조 방법, 그리고 반도체 장치를 포함하는 전자 시스템 (내용: Channel hole BCD 봑보를 위한 support poly replacement), (출원번호: P20230101840)