Research

Modern wireless systems face fundamental challenges in high-mobility environments, i.e., vehicles, trains, and low-earth orbit (LEO) satellites, where rapid channel variations degrade conventional OFDM-based waveforms. Orthogonal Time Frequency Space (OTFS) modulation addresses this by operating in the delay-Doppler (DD) domain, where the channel appears sparse and approximately time-invariant, enabling more robust and spectrally efficient communication in dynamic propagation conditions. OTFS has spurred a broader family of delay-Doppler domain waveforms, each offering different implementation tradeoffs: Orthogonal Delay-Doppler Division Multiplexing (ODDM), Orthogonal Time Sequency Multiplexing (OTSM) and Affine Frequency Division Multiplexing (AFDM). Together, these waveforms represent a rich design space for high-mobility communications.

Despite their theoretical appeal, delay-Doppler waveforms have yet to find their way into 6G standardization, and the primary obstacle is receiver complexity. Unlike OFDM, where equalization can be performed efficiently in the frequency domain, these waveforms require processing over a two-dimensional delay-Doppler grid, leading to significantly higher computational demands, larger memory requirements, and increased latency due to the longer frame durations inherent to the delay-Doppler domain. Our research aims at addressing these fundamental barriers, developing receiver algorithms and system designs that bring the practical complexity of delay-Doppler waveforms closer to what real deployments can sustain.

Beyond complexity, several other challenges must be resolved before these waveforms can be deployed at scale. In MIMO-OTFS systems, spatial correlation among antenna elements complicates detection and reduces the effective diversity gain, calling for joint spatial and delay-Doppler processing strategies. Low-complexity detection and reliable channel estimation remain open problems, particularly as the number of antennas and the size of the delay-Doppler grid grow. A further and less explored challenge arises in block time-varying (BTV) channels, where the delay and Doppler parameters of each propagation path are not static over an entire frame but vary across subframes. Initial studies show that such channel dynamics can actually be exploited, i.e., BTV channels offer higher diversity than their time-invariant counterparts, with diversity order growing with the number of subframes. This opens an interesting diversity-latency tradeoff: processing subframes independently reduces latency but harvests only partial diversity, while joint processing across subframes recovers full diversity at the cost of increased receiver delay. Understanding and exploiting this tradeoff is a central theme of our research.

The next generation of wireless networks is expected to simultaneously support high-reliability communication and high-resolution sensing within a unified system and shared spectrum. A key challenge lies in designing receivers and waveforms that serve both functions without significant compromise to either. OTFS is a natural candidate for ISAC, its delay-Doppler representation directly encodes target range and velocity as sparse channel coefficients, making sensing information extractable from the same signal used for data transmission, a property conventional OFDM-based waveforms cannot offer as cleanly.

Our research aims to develop joint channel estimation, detection, and sensing frameworks that exploit this shared delay-Doppler structure, and to explore unified waveform designs that harmonize communication and sensing requirements in high-mobility environments.

Model-driven AI approaches, which embed domain knowledge and physical layer structure into the learning framework, offer a principled alternative to purely data-driven black-box methods across a range of tasks including channel estimation, detection, synchronization, and interference mitigation. By incorporating the underlying signal processing model into the network architecture or training objective, such approaches achieve better generalization, require less training data, and produce behavior that is interpretable and trustworthy.

Our research explores model-driven AI for communications with two guiding principles. First, explainability: the learned behavior should be understandable and validatable in the context of the underlying communications problem, not simply empirically effective. Second, hardware awareness: models must be compact, low-complexity, quantization-friendly, and scalable to deployment on real embedded platforms, ensuring that accuracy gains do not come at the cost of implementability.

Translating advanced physical layer algorithms into deployable hardware requires careful co-design of the algorithm and its architecture. Our research focuses on the design of all-digital transceiver architectures for next-generation wireless systems, targeting ASIC implementation as the ultimate realization goal. A central concern is developing low-complexity, parallel transmit and receive architectures that meet the throughput and latency demands of 6G while remaining area and power efficient.

Detection, equalization, and channel estimation blocks must be redesigned from the ground up with hardware constraints in mind, i.e., fixed-point arithmetic, pipelined datapath structures, and memory-efficient implementations that scale with the number of antennas and users. For delay-Doppler waveforms such as OTFS, the two-dimensional nature of the input-output relation introduces additional architectural challenges that require novel approaches to data scheduling and processing parallelism. Low-complexity timing and carrier frequency synchronization circuits are equally critical, as synchronization errors propagate through the entire receiver chain and must be resolved with minimal hardware overhead before any detection or estimation can take place.

Theoretical guarantees and simulation results are necessary but not sufficient. Real systems must ultimately be validated under practical conditions. Our research aims to bridge this gap through prototyping on software-defined radios (SDRs), RFSoCs, and FPGA platforms, combined with RF test equipment, to take algorithms developed in simulation and validate them through over-the-air testing. This step exposes implementation challenges that are invisible in simulation, including hardware impairments, timing mismatches, and real channel variability, and informs the final push toward ASIC realization.