1. Ko-Chi Kuo and Chi-Wei Wu (2014, Feb). A 5 Ghz LC-VCO frequency synthesizer for unlicensed band of WiMAX. Expert Systems with Applications, 41(2), 622-634. NSC 101- 2221-E-110-098.

2. Ko-Chi Kuo, Shun-Dao Lin, and Hsiao-Han Hou (2012, Aug). A Current Reused Voltage-Controlled Oscillator with Balanced Enlarged Amplitude Via Decoupling Capacitance Adoption, MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 1626-1629. NSC 99-2220-E110-009.

3. Ko-Chi Kuo, Yi-Hsi Hsu (2012, Jan). A 120-420 MHz delay-locked loop with multi-band voltage-controlled delay unit. International Journal of Circuit Theory and Applications, vol. 40, pp49-63.

4. Ko-Chi Kuo and Chi-Wei Wu, “A Switching Sequence for Linear Gradient Error Compensation in the DAC Design,” IEEE Transactions on Circuits & Systems II: Express Briefs, Vol. 58, No. 8, pp. 502-506, August, 2011

5. Ko-Chi Kuo and Chi Wen Chou, “Low Power and High Speed Multiplier Design with Row Bypassing and Parallel Architecture,” Microelectronics Journal, vol. 41, No. 10, pp. 639-650, October, 2010.

6. Ko-Chi Kuo and Hsing-Hui Wu, “A low voltage, high linear, and tunable triode transconductor,” IEICE Electronics Express, Vol. 6, No. 14, pp. 1039-1044, July 25, 2009.

7. Ko-Chi Kuo, “A 2.4 GHz Low Phase Noise Frequency Synthesizer for WiMAX Applications,” IEICE Electronics Express, Vol. 8, No. 12, pp. 938-943, June 25, 2011

8. Ko-Chi Kuo and Adrian Leuciuc, “A Linear MOS Transconductor Using Source Degeneration and Adaptive Biasing,” IEEE Transactions on Circuits & Systems II: Analog & Digital Signal Processing, Vol. 48, No. 10, pp. 937-943, October 2001.

1. Ko-Chi Kuo, Ying-Ju Sung, A 12-bit 1GS/s Current Steering DAC with the Appointed and Thermometer coding scheme , pp. 1-2, The 18th IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2022), Shenzhen, China, on November 11-13, 2022.

2. Ko-Chi Kuo, Hsiung-Yu Chi, A 8-bit 300MHz Domino Based Successive Approximation Register ADC , pp. 1-2, The 19th International SoC Design Conference (ISOCC 2022) , Gangneung-si, Gangwon-do, South Korea on October 19-22, 2022.

3. Ko-Chi Kuo, Hau-Cheng Hou, Deep Neural Network Accelerator Design for the Multi-task, High performance, and Energy-efficient Edge Computing, pp.1-2, ICCSS 2021 International Conference on Circuits, Systems and Simulation (ICCSS 2021), in University Putra Malaysia, Kuala Lumpur, Malaysia on May 26-28, 2021.

4. Ko-Chi Kuo, A Novel Linear-Logarithmic Active Pixel CMOS Image Sensor with Wide Dynamic Range, pp.1-2, the 2021 IEEE International Midwest Symposium on Circuits & Systems, Michigan, USA, August 9-11,2021.

5. Ko-Chi Kuo, A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process, pp. 1-2, The 18th International SoC Design Conference (ISOCC 2021).Jeju, South Korea, Oct. 6-9, 2021.

6. Ko-Chi Kuo, A 10-bit 250 MS/s Binary Search and Two channel SAR ADC by a two-bit per Conversion with Error Tolerance Ability, IEEE International Conference on Consumer Electronics, pp.1-4, Oct. 6-9, 2019, The 16^th International SoC Design Conference, Jeju, Korea,

7. Ko-Chi Kuo, A High Speed Low Power Pipelined SAR Analog to Digital Converter, pp. 1-4, June 16-19, the 17^th IEEE International Conference on IC Design and Technology, Suzhou, China,

8. Ko-Chi Kuo, Fast Locking Technique by Using a Programmable Operational Transconductor for a Phase Lock Loop Design, pp. 1-4, June 16-19, the 17^th IEEE International Conference on IC Design and Technology, Suzhou, China.

9. Hsu-Kang Dow, Ing-Jer Huang, Robert Rieger, Ko-Chi Kuo, Lan-Yuen Guo, Shih-Jung Pao, A Bio-Sensing System-on-Chip and Software for Smart Clothes, IEEE International Conference on Consumer Electronics, pp.1-4, Jan. 9-12, 2019, Las Vegas, USA, NARL-LOT-106-005.

10. Ko-Chi Kuo, A 5th order Gm-C filter design with tuning transconductor. IEEE International Conference on Applied System Innovation, pp. Sapporo, Japan, May 13-17, 2017, Sapporo, Japan.

11. Ko-Chi Kuo (2017, May). A 1.2V 10 bits 100-MS/s Analog-to-Digital Converter with a 8-stage pipeline and a 2 bits flash ADC. 2017 IEEE International Conference on Applied System Innovation , Sapporo, Japan.

12. Ko-Chi Kuo “The Implementation of Homeplug AV System,” IEEE International Conference on IC Design and Technology, pp. Ho Chi Minh City, Vietnam, June 27-29, 2016.

13. Ko-Chi Kuo and Sz-Hsien Li , “A Wide-Range and Harmonic-Free SAR All-Digital Delay Locked Loop,” International Symposium on Communications and Information Technologies, pp. 197-200, Nara, Japan, October 7-9, 2015.

14. Ko-Chi Kuo and Chih-Wei Wu , “Power Saving Technique for Thermometer-code Digital-to-Analog Converters,” International Symposium on Communications and Information Technologies, pp. 205-208, Nara, Japan, October 7-9, 2015.

15. Ko-Chi Kuo and Chi-Wei Wu, “An Fast Lock Technique for Wide Band PLL Frequency Synthesizer Design,” 2014 International Conference on Information Science, Electronics and Electrical Engineering, pp. 759-763, Sapporo City, Japan, April 26-28, 2014.

16. Ko-Chi Kuo and Chi-Wei Wu, “An 802.15.4a Wide Band Frequency Synthesizer for 5GHz ISM Band Health Care Applications,” 2014 IEEE International Symposium on Bioelectronics and Bioinformatics , pp. Chung-Li, Taiwan, April 11-14, 2014

17. Ko-Chi Kuo and Chi-Wei Wu, “Capacitive Dynamic Comparator with Low Kickback Noise for Pipeline ADC,” 2013 IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 365-368, Hong Kong, June 3-5, 2013.

18. Ko-Chi Kuo and Chi-Wei Wu, “A Low Phase Noise VCO for 5-GHz WiMAX/WLAN Frequency Synthesizer,” 2013 IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 365-368, Hong Kong, June 3-5, 2013

19. Ko-Chi Kuo, Chung-Yuan Chang and Si-Hsien Li, “Low Power Delay Locked Loop with All Digital Controlled SAR Delay Cell,” 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp. 120-123, Kaohsiung, Taiwan, December 2-5, 2012.

20. Ko-Chi Kuo, Shan-Yu Chen, and Shih-Min Tseng, “High Linear Transconductor for Multiband CMOS Receiver,” 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp. 535-538, Kaohsiung, Taiwan, December 2-5, 2012.

21. Ko-Chi Kuo and Hsun-Chia Hsu, “Power Line Communication Chip Design with Data Error Detecting/Correcting and Data Encrypting/Decrypting Ability,” 2012 IEEE International Symposium on Intelligent Signal Processing and Communication Systems, pp. 674-677, Tamsui, New Taipei City, Taiwan November 4-7, 2012.

22. Ko-Chi Kuo and Hsueh-Ta Ko, “Low Power Design Flow with Static and Statistical Timing Analysis,” 2012 IEEE International Symposium on Intelligent Signal Processing and Communication Systems, pp. 798-801, Tamsui, New Taipei City, Taiwan November 4-7, 2012.

23. Tzung-Je Lee, Wayne Luo, Shang-Hsien Yang, Ming-Hung Shih, Ko-Chi Kuo, and Chua-Ching Wang “2.45 GHz ZigBee Receiver Frontend for HAN With Smart Meter,” 2011 International Symposium on Integrated Circuits, pp. 480-483, Singapore, December 12-14, 2011.

24. Ko-Chi Kuo, “A Wide Tuning Range 2.2 to 2.8GHz VCO with the Phase Noise Enhanced Techniques,” 2011 Asia-Pacific Microwave Conference, pp. 781-784, Melbourne, Australia, December 5-8, 2011.

25. Ko-Chi Kuo and Sheng-Quane Chen, “Low Power Level Shifter and combined with Logic Gates,” 2010 IEEE Asia Pacific Conference on Circuits and Systems, pp. 324-327, Kuala Lumpur, Malaysia, December 6-9, 2010.

26. Ko-Chi Kuo, Jia-Wei Guo, and Yu-Hao Ou,“A fully digital modulator/demodulator for Power Line Communication (PLC),” 2010 IEEE Asia Pacific Conference on Circuits and Systems, pp. 835-838, Kuala Lumpur, Malaysia, December 6-9, 2010.

27. Ko-Chi Kuo and Bo-Hua Chen, “A 100M/s s 12-bit 1.8V Low Power Switched Capacitor Class A/B Sample-And-Hold Amplifier,” International Symposium on Next-Generation Electronics, pp. 162-165, Kaohsiung, Taiwan, November 18-19, 2010.

28. Ko-Chi Kuo and Chi-Wei Wu, “Digital to Analog Converter for the Analog Front End of the WiMAX Applications,” International Symposium on Communications and Information Technologies, pp. 53-57, Tokyo, Japan, October 26-29, 2010.

29. Ko-Chi Kuo and Ming-Jing Chen, “5 GHz Phase Locked Loop with Auto Band Selection,” IEEE Asia Pacific Conference on Circuits and Systems, pp.550-553, Macao, China, November 30-December 3, 2008.

30. Liang-Bi Chen, Tsung-Yu Ho, Ing-Jer Huang, Yun-Nan Chang, Steve W. Haga, Jin-Hua Hong, Shen-Fu Hsaio, Shiann-Rong Kuang, Ko-Chi Kuo, and Chung-Nan Lee, “The Development of an Energy-awared Mobile 3D Graphics SoC with Real-time Performance/Energy Monitoring and Control,” 2008 International SoC Design Conference, pp. 1234-1237, Busan, Republic of Korea, November 24-25, 2008.

31. Ko-Chi Kuo and Yi-His Hsu, “A Low Power Multi-band Selector DLL with Wide-Locking Range,” IEEE International Conference on IC Design and Technology, pp. 25-28, Minatec Grenoble, France, June 2-4, 2008.

32. Ko-Chi Kuo and Hsing-Hui Wu, “A Low Voltage, Highly Linear, and Tunable Triode Transconductor,” IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 365-368, Tainan, Taiwan, December 20-22, 2007.

33. Ko-Chi Kuo and Feng-Ji Wu, “A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-mm CMOS Technology,” 2006 IEEE Asia Pacific Conference on Circuits and Systems, pp. 214-217, Singapore, December 4-6, 2006.

34. Ko-Chi Kuo and Chi-Wen Chou, “Low Power Multiplier with Bypassing and Tree Structure,” 2006 IEEE Asia Pacific Conference on Circuits and Systems, pp. 602-605, Singapore, December 4-6, 2006.

35. Ko-Chi Kuo and Feng-Ji Wu, “A CMOS High-Speed Nine-Stage Programmable Counter,” International Multi Conference of Engineer and Computer Scientist, pp. 213-216, Hong Kong, China, June 20-22, 2006.

36. Ko-Chi Kuo and Chi-Wen Chou, “A Low-Power Multiplier with Bypassing Logic and Operand Decomposition,” International Multi Conference of Engineer and Computer Scientist, pp. 217-220, Hong Kong, China, June 20-22, 2006.

37. Ko-Chi Kuo, “High Speed CMOS Multiplier Using CVTL Technique”, 2005 International Conference on Communications, Circuits and Systems -Proceedings, Vol. 2, pp. 1070-1074, Hong Kong, China, May 27-30, 2005.

38. Ko-Chi Kuo and Bradley S. Carlson, “High Performance CMOS Programmable Logic Array Design,” Midwest Symposium on Circuits and Systems, Vol. 2, pp. 568-571, Dayton, OH, USA, August 14-17, 2001.

39. Ko-Chi Kuo and Bradley S. Carlson, “High Performance CMOS Static Logic Circuit Design,” 2001 Midwest Symposium on Circuits and Systems, Vol. 2, pp. 598-601, Dayton, OH, USA, August 14-17, 2001.

40. Ko-Chi Kuo and Adrian Leuciuc, “A novel linear tunable MOS transconductor,” 2000 Midwest Symposium on Circuits and Systems, Vol. 1, pp. 462-465, Lansing, MI, USA, August 8-11, 2000.