HSG-HLS

HSG Feature has been implemented as a Simulink block to enable High-Level Synthesis (HLS) using Simulink Computer Vision, Vision HDL and HDL Coder toolboxes. The complete framework includes SVM training and testing routines as well. The full framework will be available for download after acceptance of a submitted paper. At the moment, only generated Verilog HDL code for the HSG IP core is available for download. It uses Xilinx AXI-4 streaming protocol.