Publications
2023
[J1] J. Wang, R. Gao, H. Zheng, H. Zhu, and C.-J. R. Shi, "SSGCNet: A sparse spectra graph convolutional network for epileptic EEG signal classification" IEEE Transactions on Neural Networks and Learning Systems, vol. 34, 2023.
[J2] H. Ren, D. Ye, B. Chen, W. Gong, X. Jin, R. Xu, L. Lyu, L. Xu, and C.-J. R. Shi, "A 19-uW blocker-tolerant wake-up receiver with -90-dBm energy-enhanced sensitivity", IEEE Transactions on Microwave Theory and Techniques, vol. 71, no. 10 pp. 4377-4392, Oct 2023 (Extended Version of RFIC 2022 paper C1]
[J3] Y. Wang, Z. Zhao, X. Jin, H. Zheng, M. Nie, Q. Zou, and C.-J. R. Shi, ""AutoMap: Automatic mapping of neural networks to deep learning accelerators for edge devices, " IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 42, no.9 pp. 2994-3006, Sept. 2023.
[J4] G. Mu, L. Lyu, D. Ye, and C-J. R. Shi, "A chopper amplifier with a low duty-cycle sub-sampling in the switched-capacitor integrator for noise reduction", Electronic Letters, vol. 59, no. 7, pp. 1-3, Apr. 2023. [pdf]
[J5] Y. Wang, T. Guan, D. Niu, Q. Zou, H. Zheng, C.-J. R. Shi and Y. Xie, ``Accelerating distributed GNN training by codes", IEEE Transactions on Parallel and Distributed Systems , vol. 34, no. 9, Sept. 2023.
[J6] J. Wang, S. Liang, J. Zhang, Y. Wu, L. Zhang, R. Gao, D. He and C.-J. R. Shi, ``EEG signal epilepsy detection with a weighted neighbor graph representation and two-stream graph-based framework", IEEE Transactions on Neural Systems and Rehabilitation Engineering , vol. 31, pp.3176-3184, 2023
[C1] R. Gan, L. Lyu and C.-J. R. Shi ,``A 7-channel bio-signal analog front end employing single-end chopping amplifier achieving 1.48 NEF", in ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC) , Milan, Italy, Sept 2023.
[C2] J. Yang, L. Lyu, Z. Dong, H. Ren and C.-J. R. Shi, ``A 28-nW noise-robust voice activity detector with background aware feature extraction", in 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC) , Nov. 2023.
2022
[J1] Z. Zhao, Y. Wang, Q. Zou, T. Xu, F. ao, J. Zhang, X. Wang, C.-J. R. Shi, J. Luo, and Y. Xie, "The spike gating flow: A hierarchical structure-based spiking neural network for online gesture recognition", Frontiers in Neuroscience, Nov. 2022.
[J2] R. Xu, D. Ye, and C.-J. R. Shi, "Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors" IEEE Transactions on Circuits and Systems-I :Regular Papers, vol. 69, no. 7, pp. 2832-2844, July 2022, doi: 10.1109/TCSI.2022.3161763.
[J3] R. Xu, D. Ye, and C.-J. R. Shi, "A 2.0-2.9 GHz digital ring-based injection-locked clock multiplier using a self-alignment frequency tracking loop for reference spur reduction", Integration, the VLSI Journal, vol. 84, pp. 1-11, May 2022 (Extended Version of RFIC 2020 paper C2]
[J4] Y. Wang, Q. Zou, Y. Tang, Q. Wang, J. Ding, X. Wang, and C-J. R. Shi, "SAIL: A Deep Learning based System for Automatic Gait Assessment from TUG Videos", IEEE Transactions on Human-Machine Systems, vol. 52, no. 1, pp. 110-122, Feb. 2022. [pdf]
[C1] H. Ren, D. Ye, B. Chen, X. Jin, W. Gong, R. Xu, and C.-J. R. Shi , "915MHz 19μW Blocker-Enhanced Wake-Up Receiver with Frequency-Hopping Two-Tone Modulation Achieving 53dB Tolerance to In-Band Interference", IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver CO, June 19-21, 2022.
[C2] R. Gang, L. Lyu, G. Mu, and C-J. R. Shi, "A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range”, IEEE Custom Integrated Circuits Conference (CICC), April 24-27 2022, Newport Beach, CA, USA.
[C3] R. Xu, D. Ye, S. Li, and C.-J. R. Shi, ``A 0.021mm^2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency,'' IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2022.
2021
[J1] C. Liu and C.-J. R. Shi, “Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications”, IEEE Trans on Circuits and Systems-II, vol. 68, no. 5, pp. 1705-1709, 2021. [pdf]
[J2] D. Ye, R. Xu, and C.-J. R. Shi, `A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain,'' IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3360-3374, 2021. [pdf]
[C1] D. Ye, Y. Tu, W. Gong, R. Xu and C. –J. R. Shi, ``A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference", in IEEE Asia Solid-State Circuits Conference, Busan, Korea, Nov 7-10, 2021.
[C2] S. Liu, Z. Zhao, Y. Wang, Q. Zou, Y. Zhang and C. -J. R. Shi, "Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing" in 31st ACM Great Lakes Symposium on VLSI, June 22-June 25, 2021.
[C3] C. Liu, C. Zhao, and C.-J. R. Shi, “A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse ", Proc. IEEE International Symp. Circuits and Systems (ISCAS), Daegu, Korea, May 22-28, 2021
[C4] C. Liu and C.-J. R. Shi, “Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications”, Proc. IEEE International Symp. Circuits and Systems (ISCAS), Daegu, Korea, May 22-28, 2021. (Also appeared in IEEE TCAS-II 2021 J1)
[C5] G. Mu, D. Ye, L. Lyu, X. Zhao, and C. –J. R. Shi, ``An 8-Channel Analog Front-End with a PVT-Insensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording", IEEE Custom Integrated Circuits Conference (CICC), Apr 25-30, 2021.
2020
[J1] H. Zhu, C. Chen, S. Liu , Q. Zou , M. Wang , L. Zhang, X. Zeng , and C.-J. R. Shi, ''A communication-aware DNN accelerator on ImageNet using in-memory entry counting based algorithm-circuit- architecture co-design in 65nm CMOS ", IEEE Journal on Emerging and Selected Topics on Circuits and Systems (JETCAS), vol. 10, no. 3, pp. 283-294, Sept 2020. [pdf]
[J2] L. Lyu, D. Ye, and C.-J. R. Shi, “A 340 nW/Channel 110 dB PSRR neural recording analog front-end using replica-biasing LNA, level-shifter assisted PGA, and averaged LFP servo loop in 65nm CMOS ", IEEE Transactions on Biomedical Circuits and Systems, vol.14 , no. 4, pp. 811-824, Aug 2020 [pdf] .
[J3] A. Wang and C.-J. R. Shi, “Analysis of passive charge sharing based segmented SAR ADCs,” IEEE Transactions on VLSI Systems, vol. 28, no. 5, pp. 1195-1206, May 2020. [pdf]
(J4) L. Lyu, D. Y e, R. Xu, G. Mu, H. Zhao, Y. Xiang, Y. Tu, Y. Zhang, and C.-J. R. Shi, “A fully-integrated 64-channel wireless neural recording SoC achieving 110 dB AFE PSRR and supporting 54Mb/s symbol rate, meter-range wireless data transmission", IEEE Transactions on Circuits and Systems-II, vol.67 , no. 5, pp. 831-835, May 2020. [pdf] (Best Student Paper Award)
[J5] D. Ye, Y. Wang, L. Lv, Y. Xiang, H. Min, and C.-J. R. Shi, `A wireless power and data transfer receiver achieving 75.4% effective power conversion efficiency and support 0.1% modulation depth for ASK demodulation ,'' IEEE Journal of Solid-State Circuits, vol. 55, no. 5, pp. 1386-1499, May 2020. [pdf]
[J6] H. Zhu, Y. Wang, and C.-J. R. Shi, ``Tanjie: A general-purpose neural network accelerator with a unified crossbar architecture ,'' IEEE Design & Test, vol 37, no. 1, pp. 56-63, Feb. 2020. [pdf]
[J7] L. Lv, Y. Wang, C. Chen, and C.-J. R. Shi, `A 0.6V 1.07uW/channel neural interface IC using level-shifted feedback,'' Integration, the VLSI Journal, vol. 79, pp. 51-59, Jan. 2020 . [pdf]
(C1) R. Xu, D. Ye, and C.-J. R. Shi, "A 2.0-2.9 GHz digital ring-based injection-locked clock multiplier using a self-alignment frequency tracking loop for reference spur reduction", Proceedings of IEEE Radio Frequency Integrated Circuits Symposium. Los Angles, CA, USA, June 21-23 2020. (Extended version appeared in Integration, the VLSI Journal May 2022 J1)
(C2) Y. Wang, F. Chen, L. Song, C.-J. R. Shi, H. Li and Y. Chen, “ReBOC: Accelerating block-circulant neural networks in ReRAM ”, Proceedings of the Design, Automation and Test in Europe (DATE), Grenoble, France, March 9-13, 2020.
(C3) S. Liu, H. Zhu, C. Chen, L. Zhang, and C-J R. Shi, “ XNORAM: An efficient computing-in-memory architecture for binary convolutional neural networks with flexible dataflow mapping ”, Proc. IEEE International Conf. Artificial Intelligence Circuits and Systems (AICAS), Genova, Italy, March 23-25, 2020.
(C4) L. Lyu, D. Ye, R. Xu, G. Mu, H.Zhao, Y. Xiang, Y. Tu, Y.Zhang, and C.-J. R. Shi, “A fully-integrated 64-channel wiireless neural recording SoC achieving 110 dB AFE PSRR and supporting 54Mb/s symbol rate, meter-range wireless data transmission", Proc. IEEE International Symp. Circuits and Systems (ISCAS), Seville, Spain, May 17-20, 2020. (Also appeared in IEEE TCAS-II May 2020 J2)
(C5) Y. Tu, R. Xu, L. Lyu, D. Ye and C.-J. R. Shi, “A 400MHz 8-bit 1.75-ps resolution pipelined two-step time-to-digital converter with dynamic time amplification”, Proc. IEEE International Symp. Circuits and Systems (ISCAS), Seville, Spain, May 17-20, 2020.
2019
[J1] C. Chen, X. Liu, H. Peng, H. Ding, and C.-J. R. Shi, “iFPNA: A flexible and efficient deep learning processor in 28nm CMOS using a domain-specific instruction set and reconfigurable fabric,” IEEE Journal on Emerging and Selected Topics on Circuits and Systems (JETCAS), vol. 9, no. 2, pp. 346 - 357, June 2019. [pdf]
[J2] C.-J. R. Shi and A. Wang, “Analysis of bitwise and sample-wise switched passive charge sharing SAR ADCs,” IEEE Transactions on VLSI Systems, vol. 27, no. 9, pp. 1977-1989, Sept. 2019. [pdf]
[J3] A. Wang, C. Chen, C. Liu, and C.-J. R. Shi, "A 9-bit resistor-based highly-digital temperature sensor with a SAR-quantization embedded differential low-pass filter in 65nm CMOS consuming 88pJ with a 2.5 μs conversion time ", IEEE Sensors Journal, vol. 19, no. 17, pp. 7215-7225, Sept. 2019. [pdf]
(C1) C. Li, K. Jia, D. Shen, C.-J. R. Shi, and H. Yang, “Hierarchical representation learning for bipartite graphs ”, Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, Main Track. pp, 2873-2879, Aug. 10-16, 2019, Macao, China (acceptance rate: 13%). [pdf]
(C2) D. Ye, R. Xu, L. Lyu, and C-J R. Shi, “A 2.46GHz, -88dBm sensitivity CMOS passive mixer-first nonlinear receiver with >50dB tolerance to in-band interferer”, Proc. IEEE International Symp. Circuits and Systems (ISCAS), Sapporo, Japan, May 26-29, 2019.
(C3) L. Lyu, D. Ye and C.-J. R. Shi, “A 340nW/channel neural recording analog front-end using replica-biasing LNAs to tolerate 200mVpp interfere from 350mV power supply”, Proc. IEEE International Symp. Circuits and Systems (ISCAS), Sapporo, Japan, May 26-29, 2019 (Best Paper Award, IEEE BioCAS Track).
[C4] A. Wang, C. Chen, and C.-J. R. Shi, ``A 9-bit resistor-based all-digital temperature sensor with a SAR-quantization embedded differential low-pass filter in 65nm CMOS consuming 57pJ with a 2.5 $\mu$s conversion time ,'' in IEEE Custom Integrated Circuits Conference (CICC) , Austin, TX, Apr. 14-17, 2019. (An extended version appeared as a journal paper published in IEEE Sensors Journal in 2019)
[C5] D. Ye, R. Xu, and C.-J. R. Shi, ``A 2.4GHz 65nm CMOS mixer-first receiver using 4-stage cascaded inverter-based envelop-biased LNAs achieving 66 dB in-band interference tolerance and 83 dBm sensitivity,'' in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2019.
2018
[J1] C. Chen, H. Ding, H. Peng, H. Zhu, Y. Wang, and C. -J. R. Shi, "OCEAN: An on-chip incremental-learning enhanced artificial neural network processor with multiple gated-recurrent-unit accelerators," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 8, no. 3, pp. 519-530, Sept. 2018. [pdf] [Google Scholar]
[J2] A. Wang and C.-J. R. Shi, ``A 10-bit 50-MS/s SAR ADC with 1 fJ/conversion in 14 nm SOI FinFET CMOS '', Integration, the VLSI Journal, vol. 62. pp. 246-257, June 2018. [pdf] [Google Scholar]
[C1] C. Li and C.-J. R. Shi, ``Constrained optimization based low-rank approximation of deep neural networks'', Proc. 15th European Computer Vision Conference (ECCV), Munich, Germany, Sept. 8-14, 2018. (pp. 746-761 in: Ferrari V., Hebert M., Sminchisescu C., Weiss Y. (eds) Computer Vision – ECCV 2018. ECCV 2018. Lecture Notes in Computer Science, vol. 11214. Springer, Cham) [pdf] [Google Scholar] [Conference Ranking: 3]
[C2] C. Chen, X. Liu, H. Peng, H. Ding, and C.-J. R. Shi, "iFPNA: A flexible and efficient deep neural network accelerator with a programmable data flow engine in 28nm CMOS", pp. 170-173 in Proc. 44th European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, Sept. 3-6, 2018. (Also as an ISSCC 2018 -SRP, presented by H. Peng) [pdf] (An extended version appeared as a journal paper in 2019) [Google Scholar]
[C3] C. Chen, H. Peng, X. Liu, H. Ding, and C.-J. R. Shi, "Exploring the programmability for deep learning processors: from architecture to tensorization", in Proc. 55th Annual IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, June 25-29, 2018. [Google Scholar]
[C4] A. Piao, A. Wang, and C. -. R. Shi, "Pin-efficient 12-bit 8-wire 8-level permutation coding for high-speed parallel wireline transceivers," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 27-30, 2018, [pdf] [Google Scholar]
[C5] Y. Wang, D. Ye, L. Lv, Y. Xiang, H. Min, and C.-J. R. Shi, ``A 13.56 MHz wireless power and data transfer receiver achieving 75.4 % effective power conversion efficiency with 0.1% ASK modulation depth and 9.2 mW output power,'' pp. 142-44 in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2018. [pdf] [Conference Ranking: 3] [Google Scholar]
2017
[J1] A. Wang, C. Chen, and C. -J. R. Shi, "Design and analysis of an always-on input-biased pA-current sub-nW mV-threshold hysteretic comparator for near-zero energy sensing," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 9, pp. 2284-2294, Sept. 2017. [pdf] [Google Scholar]
[J2] Y. Wang, N. Yan, H. Min, and C.-J. R. Shi, “A high-efficiency split-merge charge pump for solar power harvesting”, IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 64, no. 5, pp. 545-549, May 2017. [pdf] [Google Scholar]
[C1] C. Chen, H. Ding, H. Peng, H.Zhu, R. Ma, P. Zhang, X. Yan, Y. Wang, C.-J. R. Shi, "OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators", in Proc. 43rd European Solid-State Circuits Conference (ESSCIRC), Sept. 2017. [pdf] (Also as an ISSCC 2017 - SRP, presented by H. Ding; also appeared as a journal paper in 2018) [Google Scholar]
2016
[C1] A. Waters, A. Wang and C. -J. R. Shi, "Highly time-interleaved noise-shaped SAR ADC with reconfigurable order," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 1026-1029. [pdf] [Google Scholar]
[C2] A. Wang, A. Waters and C. -J. R. Shi, "A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 1054-1057. [pdf] (also appeared as a journal paper in 2017) [Google Scholar]
Previous publications are shown here.