Silicon Systems Research Lab

The UW Silicon Systems Research Lab  is currently focusing on energy-efficient  nanometer integrated circuit and system design for sensing, learning, communication, and computing.   In collaboration with Professor Michael Taylor, we are building in the industry state-of-art 14nm FinFET process

• RISC-V processor controlled deep learning accelerators  

• Gbps high-speed interfaces 

• Energy-efficient mixed-signal Internet-of Things sensing circuits

for enabling AI-infused edges and clouds. We are particularly embracing the open-source hardware and software initiative for system innovation. 

Our lab has previously worked intensively on methodologies and tools to automate the design and verification of mixed-signal integrated circuits,  resulting in commercial EDA tools and standards that have been used in production by the semiconductor industry, and several successful startups. For a snapshot of our prior research, check out these publications. 

SSRL welcomes undergraduate and graduate students to join our research  endeavor to shape the future of our society with better productivity, qualify of life, and equal opportunity for all.

• 8/21/2025: Cindy Liu defended her PhD thesis on  high-speed IO layout methodologies and will join Texas Instruments.

• 8/13/2025: Ailing Piao defended her PhD thesis on high-speed IO design.

• 6/15/2025: Frank Peng defended his thesis on LLM rack-scale design and simulation and joined Meta as an architect

• 9/15/2019 PhD student Frank Peng completed his internship at Microsoft.

• 6/10/2019 Aili Wang defended her PhD dissertation on low-power interface circuit design.

• 6/1/2019: Our deep learning paper accepted by 2019 JCAI.

• 12/16/2018 Dr. Chixiao Chen, Post-Doctoral Research Fellow joined Fudan University as an Assistant Professor.

• 10/17/2018 Our IoT receiver paper is accepted by ISSCC 2019.

• 07/03/2018 Our deep neural network rank reduction paper is accepted by ECCV 2018.

• 05/31/2018 Our OCEAN deep learning processor journal paper is accepted by  JETCAS.

• 05/20/2018 Our iFPNA deep learning processor circuit design paper is accepted by ESSCIRC 2018.

• 02/20/2018 Our iFPNA deep learning processor compilation work is accepted by DAC 2018.

• 01/18/2018 Our PAM-8 Serdes paper is accepted by ISCAS 2018.

• 12/01/2017 Our iFPNA circuit design is accepted to be presented in the ISSCC 2018 SRP session.

• 06/01/2017 Our sub-nW comparator IoT zero-energy sensing paper  appears in IEEE TCAS-I.

• 05/27/2017 Our OCEAN RNN deep learning processor design is presented at ESSCIRC 2017.