Silicon Systems Research Lab

The UW Silicon Systems Research Lab  is conducting cutting edge research on energy-efficient  nanometer integrated circuit and system design for sensing, learning, communication, and computing, with recent focuses on wafter-scale nanophotonic and electronic platforms for low-energy datacenter AI infra and protein sequencing.  Under the support of DARPA POSH program, DARPA IDEA program, and a generous research gift from Google,  in collaboration with Professor Michael Taylor, we designed and taped out,  in the industry state-of-art 12nm FinFET process,

• RISC-V processor controlled deep learning accelerators  

• Configurable Gbps high-speed interfaces that combines UCIE and LPDDR4X 

• Energy-efficient mixed-signal Internet-of Things sensing circuits

for enabling AI-infused edges and clouds. We are particularly embracing the open-source hardware and software initiatives for system innovation. Before returning back to UW in Fall 2025 for full-time teaching and research, Prof. Richard Shi was on leave in industry working on DARPA SPACE BACN and DARPA PIPES programs, for which he built  a team, jointly with Intel and Columbia University, and taped out successfully an 8mm x 8mm coherent digital signal processing chiplet with over 1 billon transistors in Intel's 3nm process, the most advanced digital process node in the United States,  for low earth orbit (LEO) “internet” of satellite optical communication networks, and an 8mm x 8mm EIC chiplet in GlobalFoundries '12nm process, which supports 64 wavelength multiplexing 1024 photonic transceivers,   each running at 16Gbps with 350fJ/b, with an edge density of 4Tb/mm, one of the first kind in the world.

Our lab has previously worked on methodologies and tools to automate the design and verification of mixed-signal integrated circuits,  resulting in commercial EDA tools and standards that have been used in production by the semiconductor industry, and several successful startups. For a snapshot of our prior research, check out these publications. 

SSRL welcomes undergraduate and graduate students to join our research  endeavor to shape the future of our society with better productivity, qualify of life, and equal opportunity for all.

• 8/21/2025: Cindy Liu defended her PhD thesis on  high-speed IO layout methodologies and will join Texas Instruments.

• 8/13/2025: Ailing Piao defended her PhD thesis on high-speed IO design and joined a Redmond startup on high-speed photonic IO .

• 6/15/2025: Frank Peng defended his thesis on LLM rack-scale design and simulation and joined Meta as an architect in LLM accelerator design.

• 06/15/2019 Chong Li defended his PhD on low-rank DNN and joined Apple as an architect in deep learning.

• 6/10/2019 Aili Wang defended her PhD dissertation on low-power sensing circuit design, joined UIUC/Zhejiang-U as an Assistant Professor.

• 6/1/2019: Our deep learning paper accepted by 2019 JCAI.

• 12/16/2018 Dr. Chixiao Chen, Post-Doctoral Research Fellow joined Fudan University as an Assistant Professor.

• 10/17/2018 Our IoT receiver paper is accepted by ISSCC 2019.

• 07/03/2018 Our deep neural network rank reduction paper is accepted by ECCV 2018.

• 05/31/2018 Our OCEAN deep learning processor journal paper is accepted by  JETCAS.

• 05/20/2018 Our iFPNA deep learning processor circuit design paper is accepted by ESSCIRC 2018.

• 02/20/2018 Our iFPNA deep learning processor compilation work is accepted by DAC 2018.

• 01/18/2018 Our PAM-8 Serdes paper is accepted by ISCAS 2018.

• 12/01/2017 Our iFPNA circuit design is accepted to be presented in the ISSCC 2018 SRP session.

• 06/01/2017 Our sub-nW comparator IoT zero-energy sensing paper  appears in IEEE TCAS-I.

• 05/27/2017 Our OCEAN RNN deep learning processor design is presented at ESSCIRC 2017.